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Dive into the research topics where Alvin W.Y. Su is active.

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Featured researches published by Alvin W.Y. Su.


IEEE Transactions on Very Large Scale Integration Systems | 2012

Resource-Efficient FPGA Architecture and Implementation of Hough Transform

Zhong-Ho Chen; Alvin W.Y. Su; Ming-Ting Sun

Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 × 512 test images with 180 orientations in 2.07-3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).


Expert Systems With Applications | 2008

Neural network based method for image halftoning and inverse halftoning

Win-Bin Huang; Alvin W.Y. Su; Yau-Hwang Kuo

A hybrid neural network based method for halftoning and inverse halftoning of digital images is presented. The halftone image is performed by single-layer perceptron neural network (SLPNN), and its corresponding continuous-tone image is reconstructed by radial-basis function neural network (RBFNN). The combined training procedure produces halftone images and the corresponding continuous tone images at the same time. The PSNR performance and visual image quality of these contone images achieved is comparable to the well-known inverse halftoning methods. The resultant halftone images compared with the error diffusion halftone are visually good, too. Furthermore, we apply different kinds of halftone images to a bi-level image compression method, called Block Arithmetic Coding for Image Compression (BACIC), which is better than the current facsimile methods.


Frontiers in Psychology | 2014

Complex hand dexterity: a review of biomechanical methods for measuring musical performance

Cheryl Metcalf; Thomas Irvine; Jennifer L. Sims; Yu L. Wang; Alvin W.Y. Su; David Owen Norris

Complex hand dexterity is fundamental to our interactions with the physical, social, and cultural environment. Dexterity can be an expression of creativity and precision in a range of activities, including musical performance. Little is understood about complex hand dexterity or how virtuoso expertise is acquired, due to the versatility of movement combinations available to complete any given task. This has historically limited progress of the field because of difficulties in measuring movements of the hand. Recent developments in methods of motion capture and analysis mean it is now possible to explore the intricate movements of the hand and fingers. These methods allow us insights into the neurophysiological mechanisms underpinning complex hand dexterity and motor learning. They also allow investigation into the key factors that contribute to injury, recovery and functional compensation. The application of such analytical techniques within musical performance provides a multidisciplinary framework for purposeful investigation into the process of learning and skill acquisition in instrumental performance. These highly skilled manual and cognitive tasks present the ultimate achievement in complex hand dexterity. This paper will review methods of assessing instrumental performance in music, focusing specifically on biomechanical measurement and the associated technical challenges faced when measuring highly dexterous activities.


instrumentation and measurement technology conference | 2004

Versatile PC/FPGA based verification/fast prototyping platform with multimedia applications

Yi Li Lin; Chung Ping Young; Yuan-Jui Chang; Yi-Hui Chung; Alvin W.Y. Su

For most integrated circuit (IC) design houses, building a dedicated field-programmable gate array (FPGA) verification board before the chip is tapped out is usually a requirement. The time and money spent on such boards are usually high. A versatile verification/fast prototyping platform consisting of an FPGA board and the associated System Software is presented. The FPGA board is connected to the host computer through a peripheral component interconnect interface. The System Software running on a Microsoft Windows environment is developed so that all the real-time data that were generated during the verification process can be downloaded and displayed on the host computer. Hence, the system acts like a logic analyzer with very large storage memory. Furthermore, the software provides interfaces for personal computer peripherals, such as a Universal Serial Bus camera, a computer monitor, and a soundcard, if the test data for multimedia applications are necessary. The results can be also demonstrated in real time through these devices. Because multimedia data are usually complicated, and the size is huge, the design and thorough verification are usually difficult and take lots of time. The proposed system is both versatile and convenient to use, and verification of designs becomes much easier. An MPEG-4 Simple Profile Video Encoder and a 3-D surround sound processor were realized with the proposed system. Both cases can run in real time. In this paper, the highly complicated H.264/Advanced Video Coding I-Frame encoder is also used to demonstrate the proposed system.


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2006

VLSI Implementation of a Modified Efficient SPIHT Encoder

Win-Bin Huang; Alvin W.Y. Su; Yau-Hwang Kuo

Set Partitioning in Hierarchical Trees (SPIHT) is a highly efficient technique for compressing Discrete Wavelet Transform (DWT) decomposed images. Though its compression efficiency is a little less famous than Embedded Block Coding with Optimized Truncation (EBCOT) adopted by JPEG2000, SPIHT has a straight forward coding procedure and requires no tables. These make SPIHT a more appropriate algorithm for lower cost hardware implementation. In this paper, a modified SPIHT algorithm is presented. The modifications include a simplification of coefficient scanning process, a 1-D addressing method instead of the original 2-D arrangement of wavelet coefficients, and a fixed memory allocation for the data lists instead of a dynamic allocation approach required in the original SPIHT. Although the distortion is slightly increased, it facilitates an extremely fast throughput and easier hardware implementation. The VLSI implementation demonstrates that the proposed design can encode a CIF (352 × 288) 4:2:0 image sequence with at least 30 frames per second at 100-MHz working frequency.


IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 2011

A Versatile Wireless Portable Monitoring System for Brain–Behavior Approaches

Da Wei Chang; Sheng-Fu Liang; Chung Ping Young; Fu Zen Shaw; Alvin W.Y. Su; You De Liu; Yu Lin Wang; Yi Che Liu; Jing Jhong Chen; Chun Yu Chen

It is critical to set up a precise and feasible monitoring system for a variety of animal and human studies. A multichannel wireless system for monitoring physiological signals of freely moving rats is presented. This system combines electroencephalogram (EEG) and acceleration signals, enabling the study of association between brain and behavior. A combination of EEG and accelerometers eliminates the necessity for complicated video installation as well as time-consuming and tedious analysis of recorded videos. The IEEE 802.15.4 based wireless communication frees the experimental subject from the hassle of wires and reduces wire artifacts during recording. Long-period continuous recording was possible because of the low power feature of the system. Methods for automatic wake-sleep state discrimination and temporal lobe epileptic seizure detection are also proposed to demonstrate the advantages of the system. An accuracy of up to 96.22% for the automatic discrimination of wake-sleep states is an advantage of our system. In addition, the detection of amygdala-kindling temporal lobe seizures reaches 100% with zero false alarms, greatly saving manpower in the identification of temporal lobe epilepsy.


ACM Transactions on Architecture and Code Optimization | 2010

A hardware/software framework for instruction and data scratchpad memory allocation

Zhong-Ho Chen; Alvin W.Y. Su

Previous researches show that a scratchpad memory device consumed less energy than a cache device with the same capacity. In this article, we locate the scratchpad memory (SPM) in the top level of the memory hierarchy to reduce the energy consumption. To take the advantage of a SPM, we address two issues of utilizing a SPM. First, the programs locality should be improved. The second issue is SPM management. To tackle these two issues, we present a hardware/software framework for dynamically allocating both instructions and data in SPM. The software flow could be divided into three phases: locality improving, locality extraction, and runtime SPM management. Without modifying the original compiler and the source code, we improve the locality of a program. An optimization algorithm is proposed to extract the SPM allocations. At runtime, an SPM management program is employed. In hardware, an address translation logic (ATL) is proposed to reduce the overhead of SPM management. The results show that the proposed framework can reduce energy delay product (EDP) by 63%, on average, when compared with the traditional cache architecture. The reduction in EDP is contributed by properly allocating both instructions and data in SPM. By allocating only instructions in SPM, the EDPs are reduced by 45%, on average. By allocating only data in SPM, the EDPs are reduced by 14%, on average.


international symposium on circuits and systems | 2008

Effective congestion and error control for scalable video coding extension of the H.264/AVC

Jing Xin Wang; Alvin W.Y. Su; Yi Chen Chen; Jenq-Neng Hwang

We present an effective congestion and error control mechanism for scalable video coding (SVC) extension of the H.264/AVC video dissemination over Internet. The congestion control is used to determine the appropriate number of SVC video layers based on bandwidth inference congestion (BIC) control protocol for layered multicast scenarios and the error control is achieved by unequal forward error correction (FEC) layered protection using block erasure coding. Through the real Internet streaming experiments, we demonstrate the effectiveness of the proposed layered SVC delivery, in terms of subscription layer, average packet loss rate and PSNRs, under several layered-definition scalabilities.


international conference on multimedia and expo | 2005

Dynamic Gop Structure Determination for Real-Time MPEG-4 Advanced Simple Profile Video Encoder

Yu Lin Wang; Jing Xin Wang; Yen Wen Lai; Alvin W.Y. Su

MPEG-4 advanced simple profile video provides I, P, and B-type frames in each GOP (group of pictures). To maximize the coding efficiency, it is important to determine the distribution of the three frame types, also called the GOP structure. In this paper, the GOP structure is determined dynamically in real time by using the information, such as Sad (sum of absolute difference) and Mad (mean of absolute difference), generated in the encoding process and little amount of computation is used. The algorithm first determines whether the current frame is an intra-picture or an inter-picture. If it is an inter-picture, one has to decide whether it is a P_picture or a B_picture. No more than 4 consecutive B_pictures can be employed to reduce the video buffer size. The proposed method is tested over a wide range of video sequences at different data rate conditions and produces consistent improvement compared to fixed GOP methods


IEEE Transactions on Speech and Audio Processing | 2001

A new automatic IIR analysis/synthesis technique for plucked-string instruments

Alvin W.Y. Su; Sheng-Fu Liang

In this paper, an automatic way of analyzing/synthesizing plucked-string instruments by using a simple IIR (infinite impulse response) structure is presented. The basic structure of the proposed IIR filter consists of a delay line with feedback loops pulled out from the delay line back to the input side of the filter. The feedback portion acts like a prediction filter to modify the signal for the next period such that it can be as close to the original tone as possible. The delay line and the prediction filter provide the mechanism to produce the desired pitch of the synthetic sound. The design of the coefficients for this IIR synthesizer is accomplished by using a neural network based training algorithm. The excitation signal is extracted from the original tones recorded from the target instrument. Several sets of filter coefficients are required for different synthesis stages such as the attacking part and sustain part. The proposed algorithm is tested over a wide range of plucked-string instruments. Although it requires more computation compared to some model-based approaches, the analysis work is simple and straightforward. In addition, the synthetic tone sounds very close to the correspondent original sound.

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Wei Chen Chang

National Cheng Kung University

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Yu Lin Wang

National Cheng Kung University

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Sheng-Fu Liang

National Cheng Kung University

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Tien Ming Wang

National Cheng Kung University

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Ce-Kuen Shieh

National Cheng Kung University

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Jing-Xin Wang

National Cheng Kung University

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Wei Hsiang Liao

National Cheng Kung University

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Yin Lin Chen

National Chiao Tung University

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Zhong-Ho Chen

National Cheng Kung University

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Li Su

Center for Information Technology

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