Amarendra Edpuganti

New Optimal Pulsewidth Modulation for Single DC-Link Dual-Inverter Fed Open-End Stator Winding Induction Motor Drive

The multilevel topology with dual inverters feeding both ends of an open-end stator winding of an induction motor has been introduced around two decades ago. A common-mode inductor is usually required in series with motor windings to suppress zero-sequence or common-mode currents. In case of medium voltage high-power drives, low device switching frequency operation is preferred to improve the overall system efficiency. However, it increases the harmonic distortion of machine stator currents. Therefore, the goal of our study is to propose new optimal pulse width modulation to achieve: low device switching frequency, minimal harmonic distortion of machine stator currents, and elimination of zero-sequence currents. The main idea is to select the switching angles of two inverters such that zero-sequence components are eliminated and, then, perform optimization to determine switching angles that minimize the harmonic distortion of machine stator currents. The experimental results obtained from dual two-level and dual three-level inverter fed 1.5-kW open-end stator winding IM drive demonstrated the effectiveness of a proposed modulation technique.

A Survey of Low Switching Frequency Modulation Techniques for Medium-Voltage Multilevel Converters

Multilevel converters (MLCs) have emerged as standard power electronic converters for medium-voltage high-power industrial applications. Owing to dominating device switching losses in high-power applications, it is preferable to use low device switching frequency (LDSF) modulation techniques. Then, it is possible to achieve higher device utilization, higher converter efficiency, and reduced cooling requirements. However, there exists a tradeoff between device switching frequency and harmonic distortion of converter output currents. Therefore, the main challenge for LDSF modulation techniques is to minimize the harmonic distortion of the output currents. The goal of this paper is to provide a review of various LDSF modulation techniques proposed in the literature and also discuss in detail about one of the emerging LDSF control techniques known as synchronous optimal pulsewidth modulation. Finally, challenges to LDSF modulation techniques for emerging multilevel topologies and future trends in applications of MLCs are discussed to motivate further research, to enhance the proposed LDSF techniques, and to explore for new alternatives.

Optimal Low-Switching Frequency Pulsewidth Modulation of Medium Voltage Seven-Level Cascade-5/3H Inverter

Low-switching frequency modulation of multilevel inverters for medium-voltage high-power industrial ac drives is essential to reduce switching losses and, thus, improve the overall energy efficiency of the system. However, minimizing the switching frequency increases the total harmonic distortion (THD) of machine currents. Synchronous optimal pulsewidth modulation (SOP) is an emerging technique for controlling multilevel inverters at low-switching frequency without compromising on the THD of machine currents. The goal of our experiment was to implement SOP technique for controlling seven-level cascade inverter for an induction motor drive at an average device switching frequency limited to rated fundamental frequency. First, optimal seven-level waveforms were obtained by ofline optimization assuming steady-state operating conditions. Then, the switching angles for each semiconductor device were obtained that ensure equal distribution of switching losses as well as minimal unbalance in dc-link capacitor voltages. The proposed SOP technique is validated by experimental results obtained from the seven-level cascade inverter feeding a 1.5-kW induction motor.

Optimal Low Switching Frequency Pulsewidth Modulation of Nine-Level Cascade Inverter

Synchronous optimal pulsewidth modulation (SOP) permits low switching frequency modulation of multilevel inverter for medium-voltage high-power industrial ac drives without compromising on total harmonic distortion (THD). An aim of our experiment was to operate a nine-level cascade inverter of an induction motor drive at an average device switching frequency limited to rated fundamental frequency by using SOP technique. To reduce the number of separate dc sources, a three-level diode clamped converter was used as a cell in the nine-level cascade inverter. Using SOP technique, optimal nine-level waveforms were obtained by ofline optimization assuming steady-state operation of the induction machine. The switching angles for each semiconductor switch are then obtained from optimal nine-level waveforms based on the criteria to minimize the switching frequency as well as unbalance in dc-link capacitor voltages. Experimental results obtained from the 1.5-kW induction motor drive show THD 5% for stator currents. The results indicate that SOP technique reduces the switching frequency of operation without compromising on THD.

Fundamental Switching Frequency Optimal Pulsewidth Modulation of Medium-Voltage Cascaded Seven-Level Inverter

Multilevel converters (MLCs) emerged as standard solutions for medium voltage (MV) high-power industrial ac drives. MV drives require low device switching frequency operation due to the higher switching losses of semiconductor devices. However, low device switching frequency operation leads to an increase in the harmonic distortion of machine stator currents. Therefore, there is a need to implement low switching frequency modulation technique for MLCs, which does not compromise on the harmonic distortion of machine currents. The goal of this paper is to propose a new optimal pulsewidth modulation technique for a cascaded seven level (7L) inverter such that the maximum device switching frequency is limited to the rated fundamental frequency (50/60 Hz) and all power semiconductor devices operate at identical switching frequency. Optimal switching patterns were determined offline assuming steady-state conditions. Later, switching angles for each semiconductor device are determined and stored in an FPGA controller. A low-power prototype of the 7L cascade inverter has been developed to demonstrate the proposed modulation technique. The experimental results demonstrated that the proposed optimal modulation technique maintains the quality of machine stator currents while the device switching frequency is limited to the rated fundamental frequency.

Fundamental Switching Frequency Optimal Pulsewidth Modulation of Medium-Voltage Nine-Level Inverter

A low device switching frequency operation is essential in medium-voltage (MV) high-power drives to increase semiconductor device utilization as well as to achieve higher overall system efficiency. However, there exists a tradeoff between device switching frequency and harmonic distortion of machine currents. Synchronous optimal pulsewidth modulation (SOP) is an evolving technique for controlling multilevel inverters of MV ac drives at low device switching frequency without compromising the quality of machine currents. The state-of-the-art generalized SOP algorithm for five or higher level inverters leads to unequal device switching frequency, and also, transients in machine currents are possible due to the change in the number of switching instants at higher modulation index values. The goal of our study is to propose a new SOP technique that ensures equal device switching frequency and further reduces device switching frequency compared to the generalized SOP method. Also, it is expected that machine current transients at higher modulation index values will be reduced. The proposed SOP technique has been verified experimentally on a cascade nine-level inverter-fed 1.5-kW induction motor drive.

Current-Fed Multilevel Converters: An Overview of Circuit Topologies, Modulation Techniques, and Applications

Multilevel converters (MLCs) have emerged as standard power electronic converters in high power as well as quality demanding applications. They are classified into current-fed MLCs and voltage-fed MLCs. Voltage-fed MLCs have widely researched whereas the current-fed MLCs are the recent topic of research. Based on the principle of duality between voltage and current sources, several current-fed MLCs analogous to voltage-fed MLCs have been identified. Current-fed MLCs offer several advantages in terms of high power capability, transformerless operation, short-circuit protection, and excellent quality of output current waveform. The goal of this paper is: 1) to present review of circuit topologies, modulation schemes, and applications of current-fed MLCs; and 2) to review an emerging low-device switching frequency modulation technique known as synchronous optimal pulsewidth modulation for current-fed MLCs. The circuit configuration and advantages of each topology along with various modulation techniques are discussed in detail. Compared to voltage-fed MLCs, the operation of current-fed MLCs need to satisfy additional switching constraints. A survey of classical methods for realization of these operational constraints has been done and a new generalized method has been proposed. Finally, future scope of research has been presented to encourage further development of topologies and modulation techniques for current-fed MLCs.

Optimal Pulsewidth Modulation for Common-Mode Voltage Elimination Scheme of Medium-Voltage Modular Multilevel Converter-Fed Open-End Stator Winding Induction Motor Drives

Multilevel converter topologies for open-end stator winding medium-voltage (MV) induction motor drives have been researched from the last two decades. In this paper, a dual n-level modular multilevel converter (MMC) topology has been proposed for open-end stator winding MV induction motor drives. The control requirements of the proposed system are low device switching frequency, minimal harmonic distortion of machine stator currents, elimination of common-mode voltages in machine stator windings, and maintaining floating capacitor voltages around their nominal value. Based on these requirements, an emerging modulation technique for MV induction motor drives known as synchronous optimal pulsewidth modulation has been developed for the proposed dual nL-MMC topology. The laboratory measurements from a dual three-level MMC fed 1.5-kW open-end stator winding induction motor drive demonstrate the performance of proposed technique.

A survey of low-switching frequency modulation techniques for medium-voltage multilevel converters

Multilevel converters (MLCs) have emerged as standard power electronic converters for medium-voltage high-power industrial applications. Owing to dominating device switching losses in high-power applications, it is preferable to use low device switching frequency (LDSF) modulation techniques. Then, it is possible to achieve higher device utilization, higher converter efficiency, and reduced cooling requirements. However, there exists a tradeoff between device switching frequency and harmonic distortion of converter output currents. Therefore, the main challenge for LDSF modulation techniques is to minimize the harmonic distortion of the output currents. The goal of this paper is to provide a review of various LDSF modulation techniques proposed in the literature and also discuss in detail about one of the emerging LDSF control techniques known as synchronous optimal pulsewidth modulation. Finally, challenges to LDSF modulation techniques for emerging multilevel topologies and future trends in applications of MLCs are discussed to motivate further research, to enhance the proposed LDSF techniques, and to explore for new alternatives.

New optimal pulsewidth modulation for single DC-link dual inverter fed open-end stator winding induction motor drives

The multilevel topologies of dual inverters feeding an open-end stator winding induction motor has been introduced around two decades ago. However, these topologies require common-mode inductor in series with motor windings to suppress zero-sequence or common-mode currents. In medium-voltage high power drives, low device switching frequencies are preferred to improve the overall efficiency of drive system. On the other hand, low device switching frequencies leads to higher total harmonic distortion (THD) of stator currents. Therefore, the objective of our study was to propose a new optimal pulsewidth modulation to eliminate zero-sequence currents and minimize harmonic distortion of stator currents, while operating power semiconductor devices at low device switching frequencies. The main idea is to select switching patterns such that all zero-sequence components are eliminated and then, perform optimization for every steady-state operating point to minimize the THD of stator currents. The proposed modulation has been validated on dual two-level and dual three-level inverters fed 1.5-kW open-end stator winding Induction motor drive.