Amin Akbari

A novel fast glitchless 7-3 counter with a new structure

This paper discusses about the design of a novel fast 7-3 counter for CMOS low power, high speed multiplier. In order to reduce delay and increase the speed, some changes have been made in the structure of the counters. Also the occupied area by the counter is decreased because of the less number of transistors. The delay of the proposed structure is 185ps which is simulated by HSPICE using TSMC 0.18μm CMOS technology.

A novel fast glitchless 4-2 compressor with a new structure

This article is attributed to a novel 4-2 compressor based on a new structure with a special feature of having no glitch at the output waveform. Speed enhancement is achieved through the quick production of Cout and optimum tuning of the width of utilizing transistors. The delay of the proposed structure is about 130ps in which the authenticity of our claim is proved by using the results extracted by Hspice software using CSMC 0.18μm technology.

A novel mixed-signal digital voltage mode CMOS fuzzy logic controller in 0.18μm technology

What is presented in this article is a general purpose fuzzy controller. In comparison with other structures, a novel approach is used in the fuzzifier section that brings about accuracy and speed enhancement. A new Min-Max circuit with the capability of generating minimum, maximum and both of mentioned results (utilizing a decoder) is exploited in inference engine. The defuzzifier is designed in a simple manner according to the center of area (COA) method and it acts like a variable resistor. A controller of two inputs, nine rules and one output simulated with Hspice software with level 49 parameters. The inference speed of the controller is about 18.4 MFLIPS. The controller has two inputs, nine rules and one output.

A novel high-speed 4-bit carry generator with a new structure for arithmetic operations

A new high speed 4-bit carry generator is proposed in this paper. A new structure has been introduced to reduce the delay from inputs to the outputs. Also this structure utilizes less number of transistors and it occupies smaller area size. Proposed structure has been simulated by HSPICE software in a typical 0.18 um CMOS technology and results show that there is a 500ps delay from inputs to output.

A novel method in fractional synthesizers for a drastic decrease in lock time

A 1GHz frequency divider is presented in this paper. The proposed architecture aims to minimize lock time in Phase-Locked Loops (PLLs). Proposed structure has been simulated by HSPICE software in a typical 0.18μm CMOS technology at the supply voltage of 1.8V. Simulation results show that the designed divider locks in 2-20μs which is a lower lock time compared to conventional PLLs.

An ultra high speed booth encoder structure for fast arithmetic operations

A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay of the proposed structure is about 170ps.

Fast and accurate fractional frequency synthesizer in 0.18μm technology

A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The structure has been simulated by HSPICE software in a typical 0.18um CMOS technology at the supply voltage of 1.8V. Simulation results prove that the designed frequency divider locks instantly that is a lower lock time compared to conventional PLLs.

A highly accurate fuzzifier in current mode with low power consumption

What is discussed in this article is a current mode membership function generator (MFG) which consists of digital and analog parts or in other words it is a mixed mode MFG. The proposed MFG which consumes less power and perform in high speed can generate output shapes(S, Z, triangular and trapezoidal) and by exploiting 7 switches, slope and height altering and also horizontal shifting is available. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology.

A novel mixed-signal digital CMOS fuzzy logic controller in current mode

This article discusses about a fuzzy controller. The fuzzifier is designed with a novel structure which is more suitable than other topologies and it has a high accuracy and speed. The processing unit, inference engine, is extracted out of reference [1] that is able to generate both maximum and minimum of its inputs currents simultaneously. Ultimately, the defuzzifier is simple and the center of area (COA) is used in this section. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology. The inference speed of this controller (with two inputs, one output and sixteen rules) is about 42.6 MFLIPS.

A new ultra high speed 5-2 compressor with a new structure

This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors. Additionally, the number of transistors used in this architecture (74) is less than the recent 7-2 compressors. The proposed structures delay proved by the results of the simulations applied to Hspice software using standard TSMC 0.18μm CMOS technology is about 285ps.