Amin Jarrah

Optimized FPGA based implementation of particle filter for tracking applications

Particle filter has been proven to be a very effective method for identifying targets in non-linear and non-Gaussian environment. However, particle filter is computationally intensive. So, particle filter has been implemented on FPGA by exploiting parallel and pipelining approaches to reduce the computational burden. Our optimized FPGA implementation improves up to twelve times speed up. Also more speed ups are achieved with increasing number of particles.

FPGA based architecture of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR)

Passive Bistatic Radar (PBR) exploits existing signals of opportunity from different sources such as Radio and TV signals. Extensive Cancellation Algorithm (ECA) has been proven to be a very effective way to mitigate the effects of direct signal, multipath and clutter echoes in PBR. Also, it is able to detect a moving target accurately when it comes to strong-clutter environment and long-range detection providing evidence for its robustness. However, ECA is a computationally intensive algorithm and will benefit from parallel processing and modern computational platforms such as Field Programmable Gate Arrays (FPGAs). This work involves transformation of ECA by exploring opportunities for parallel processing and elimination of any unnecessary computations and storages. ECA algorithm has been also implemented on FPGAs for high speed computation by exploiting parallel and pipelining approaches. A new software tool called Radar Signal Processing Tool (RSPT) has been developed. It allows the designer to auto-generate fully optimized VHDL representation of ECA by specifying many user input parameters through GUI. The produced VHDL code is independent of FPGA part. It is also appropriate for use with any future high performance FPGAs or ASICs to further cut down computation time. Moreover, it provides the designer a feedback on various performance parameters. This offers the designer an ability to make any adjustments to the ECA component until the desired performance of the overall System on Chip (SoC) is achieved. The computation time of our transformed/optimized algorithm has improved by a factor of 3.8. Its FPGA implementation offers a speed up of 18 over CPU.

A Parallel Implementation of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR) on a GPU

Passive Bistatic Radar (PBR) receives high interest because of exploiting existing signals of opportunity from the surrounding environment such as TV and Radio signals. It reduces the pollution and the interference since it doesn’t require a dedicated transmitter. However, PBR needs a novel algorithm to detect the target accurately since the RF transmitted signals is not under the control of the radar designer and has a variable structure of the ambiguity function. So, novel adaptive cancellation filters such as Extensive Cancellation Algorithm (ECA) was designed which has proven to detect the target accurately. However, ECA is a computationally intensive algorithm. This work involves transformation of ECA by exploring opportunities of any computation and storage that can be eliminated. ECA algorithm also has been implemented on GPU by exploiting parallel and pipelining approaches. The computation time of our transformed algorithm has improved by a factor of 3.8. Also, the achieved speed-up of GPU over our sequentially transformed algorithm is improved by up to 20.8.

Optimized Parallel Implementation of Extended Kalman Filter Using FPGA

There are enormous numbers of applications that require the use of tracking algorithms to predict the future states of a system according to its previous accumulated states. Thus, many efficient techniques are widely adopted to estimate the future states of a system at every point in time to get the desired performance levels. Kalman filter is a popular and an efficient method for online estimations for linear measurements. Extended Kalman Filter (EKF), on the other hand, is more suited for nonlinear measurements. However, EKF algorithm is well known to be computationally intensive, and may not achieve the strict requirements of real time applications. This issue has motivated researchers to consider the use of parallel processing platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs) to meet the real time requirements. This paper provides an optimized parallel architecture for EKF using FPGA. Our approach exploits many optimization and parallel techniques such as pipelining, loop unrolling, dataflow, and inlining; and utilizes the inherently parallel architecture nature of FPGAs to accelerate the estimation process. Our experimental analyses show that our optimized implementation of EKF can achieve better results when compared to other implementations using GPU and multicore platforms. Moreover, higher performance levels can be achieved when operating on larger data sizes. This is due to our proposed optimization techniques that we have applied, and the exploited inherent parallelism among EKF operations.

Optimized parallel architecture of evolutionary neural network for mass spectrometry data processing

Evolutionary neural network (ENN) shows high performance in function optimization and in finding approximately global optima from searching large and complex spaces. It is one of the most efficient and adaptive optimization techniques used widely to provide candidate solutions that lead to the fitness of the problem. ENN has the extraordinary ability to search the global and learning the approximate optimal solution regardless of the gradient information of the error functions. However, ENN requires high computation and processing which requires parallel processing platforms such as field programmable gate arrays (FPGAs) and graphic processing units (GPUs) to achieve a good performance. This work involves different new implementations of ENN by exploring and adopting different techniques and opportunities for parallel processing. Different versions of ENN algorithm have also been implemented and parallelized on FPGAs platform for low latency by exploiting the parallelism and pipelining approaches. Real data form mass spectrometry data (MSD) application was tested to examine and verify our implementations. This is a very important and extensive computation application which needs to search and find the optimal features (peaks) in MSD in order to distinguish cancer patients from control patients. ENN algorithm is also implemented and parallelized on single core and GPU platforms for comparison purposes. The computation time of our optimized algorithm on FPGA and GPU has been improved by a factor of 6.75 and 6, respectively.

Optimized FPGA based implementation of discrete wavelet transform

Development of fast Discrete Wavelet Transformation (DWT) is desired in many real life applications. It provides time-frequency representation which gives a multi-resolution outlook of the signal. It is also used for de-noising the signal. However, the DWT is computationally intensive and requires high speed computing platform. So, it is desirable to implement DWT on FPGAs as they have a capability of offering pipelined and parallel processing architecture to achieve real time performance. In this work, an efficient implementation of the DWT method on FPGA platform is proposed for all its dimensions (1-D, 2-D and 3-D). Experimental results demonstrate that our optimized implementation can significantly outperform an equivalent implementation. Also, it shows superior performance when compared with other implementations on different platforms.

Parralelization of non-linear & non-Gaussian Bayesian state estimators (Particle filters)

Particle filter has been proven to be a very effective method for identifying targets in non-linear and non-Gaussian environment. However, particle filter is computationally intensive and may not achieve the real time requirements. So, its desirable to implement it on parallel platforms by exploiting parallel and pipelining architecture to achieve its real time requirements. In this work, an efficient implementation of particle filter in both FPGA and GPU is proposed. Particle filter has also been implemented using MATLAB Parallel Computing Toolbox (PCT). Experimental results show that FPGA and GPU architectures can significantly outperform an equivalent sequential implementation. The results also show that FPGA implementation provides better performance than the GPU implementation. The achieved execution time on dual core and quad core Dell PC using PCT were higher than FPGAs and GPUs as was expected.

Energy analysis and NoC design for heterogeneous MPSoC platform for a video application

Networks-on-chip has been seen as an interconnect solution for complex system but the performance and the energy dissipation still represent limiting factors for Multi-Processors Systems-on-Chip (MPSoC). The future handheld devices must support multimedia applications for long battery life but this type of application imposes heavy constraints in terms of energy and forces the designers to optimize all parts of the platform to achieve the desirable goals. The objective of this paper is to analyze and assess the energy dissipation for heterogeneous NoC-based MPSoC platform running a video application. It identifies bottlenecks for the entire platform. We showed that the energy dissipation appear to be the most critical factor for memory and caches not for the communication architecture as the common belief. Also, we propose a new modeling and simulation approach regarding the channel width and buffer sizing which have a strong impact on the performance and the overhead of the chip. We showed that there are some hot spots in the system regarding the channel width and buffer size must be optimized to get a better performance.

A parallel implementation of IR video processing on a GPU

A bird and bat monitoring system has been developed that uses marine radar, IR camera and acoustic recorders for wind farm applications. IR video recording is used to monitor birds and bats activity which will be useful for wildlife biologists in developing mitigation techniques to minimize impact of wind turbines on birds and bats. In order to process nocturnal migration data that is recorded from one hour after sun set to one hour before the sun rise requires high speed computations. IR video processing is computationally intensive. A parallel processing approach and use of GPU is proposed to process IR video data that will meet real time requirements. This paper examines the parallel implementation of the IR video processing on GPU.We achieved the real time requirements and the necessary performance for analyzing IR with size 704×480.

Software tool for FPGA based MIMO radar applications

Direct Data Domain (D3) algorithm is very useful in Space-Time Adaptive Processing (STAP) algorithms to mitigate the effects of multipath and interference. However, the computation of D3 is computationally intensive. A software tool is developed that is capable of auto-generating a fully optimized VHDL representation of D3 with many user input parameters without having to write a single line of VHDL code. It will provide feedback on various performance parameters such as occupied slices, maximum frequency, and dynamic range performance. So, the designer can focus on the overall SoC performance and make adjustments to the D3 as necessary. Many optimization techniques are used to improve throughput and latency.