Amin Z. Sadik

Joint Time-domain/Frequency-domain Impulsive Noise Reduction in OFDM-based Power Line Communications

Impulsive noise is one of the major challenges in power line communications and can cause serious problems in OFDM-based PLC systems. In this paper, we propose a combined Time-Domain/Frequency-domain technique for impulsive noise reduction in OFDM-based PLC systems. The performance of the proposed technique is studied against well known time-domain nonlinearities by means of computer simulations. The obtained simulation results show that the Combined TD/FD technique performs better than practically used nonlinearities and can reduce the adverse effect of impulsive noise significantly.

Power Savings Analysis of Clipping and Filtering Method in OFDM Systems

The clipping and filtering method is analyzed in terms of power savings. The analysis takes account of the gain in the amplifier efficiency due to peak-to-average-power-ratio (PAPR) reduction. Assuming a linear amplifier and a typical digital signal processor, the power savings is shown to be in the order of Watts.

On the DWT- and WPT-OFDM versus FFT-OFDM

We demonstrate simulation approaches for wavelet based OFDM, particularly in DWT and WPT-OFDM as alternative substitutions for Fourier based OFDM. We begin by constructing the models of the inverse and forward transforms, which can be flexible for substitutions in an OFDM system. We explain in detail each model and study the BER performance. The wavelet based OFDM (DWT-OFDM and WPT-OFDM) is assumed to have orthonormal bases properties and satisfy the perfect reconstruction property. We use different wavelet families and compare with conventional FFT-OFDM system. We found that the DWT-OFDM platform is superior as compared to others as it has less error rate, especially when it uses bior5.5 or rbior3.3 wavelet family.

Compressed image transmission over FFT-OFDM: A comparative study

In this work we present a comparative study for the transmission of a wavelet-compressed still image using FFT-OFDM over multipath channels with additive white Gaussian noise (AWGN). Rather than using a global threshold for the compression of the wavelet coefficients, we chose to compress the data by transmitting only the low-pass subbands from each decomposition level. 16-QAM is considered for the modulation of the data and various wavelets are considered. A comparison is also performed between the common discrete cosine transform (DCT) compression method and the DWT to compare accuracy and efficiency of data transmission using the two methods. The performance criteria for our compression methods include the compression ratio and relative root-mean-squared (RMS) error of the received data.

POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters

While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {−1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.

Simple discrete bit-loading for OFDM systems in power line communications

Adaptive bit-loading algorithms can improve the performance of OFDM systems significantly. The tradeoff between the algorithms performance (optimum solution) and the computational complexity is essential for implementation of loading algorithms. In this paper, we present a low complexity non-iterative discrete bit-loading algorithm to maximize the data rate subject to specified target BER and uniform power allocation. Simulation results show that the proposed algorithm outperforms the equal-BER loading and achieves similar rates to incremental allocation, yet with much lower complexity.

Short word-length LMS filtering

The distinctive advantage of short-word-length systems (single-bit, two-bit, or ternary), namely, the hardware implementation simplicity, has not been put into effect due to its unresolved LMS adaptivity problem. The conventional LMS family of adaptive algorithms fail to converge if translated to the short-word-length domain. In this paper we propose a 2-bit-domain LMS adaptive filtering structure for noise cancelling where all input, output, and filter coefficients are in 2-bit format. The proposed structure is designed and analyzed, and its performance has been evaluated (in comparison to the conventional Widrow-Hoff multi-bit LMS algorithm) in terms of convergence properties, signal-to-noise improvement, and computational complexity. Simulation results showed that the proposed 2-bit adaptive structure exhibits performance that is equivalent to the infinite-precision LMS algorithm.

Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter

We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9dB at the cost of a doubling in hardware area.

One-Iteration-Clipping-Filtering (OICF) scheme for PAPR reduction of OFDM signals

A new scheme for iterative clipping and filtering (ICF) method is proposed for PAPR (peak-to-average power ratio) reduction of OFDM (orthogonal frequency division multiplexed) signals. The proposed one-iteration-clipping-filtering (OICF) scheme achieves target PAPR in one iteration, instead of K (>1) iterations as in conventional ICF method. An empirical expression is derived to scale original clipping threshold so that the target PAPR can be achieved in first iteration.

Single-Bit and Conventional FIR Filter Comparision in State-of-Art FPGA

The performance/area characteristics of a Sigma Delta Modulated Ternary FIR filter and a conventional FIR filter are compared. The implementation of both filters has been carried out in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. At a similar spectral performance, the ternary FIR filter achieved 40% higher performance than its conven-tional equivalent using a 12x12 bit multiplier with much lower I/O and a slightly smaller area. This performance ratio was increased to 70% in pipelined mode. Clock speeds in excess of 200MHz at 32 OSR were achieved on a low-cost FPGA and over 400MHz on a high-performance device.