Amine Bermak

A Sub-

An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 μm CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) signals can be obtained through proper transistor sizing. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 333 samples/s and achieves an inaccuracy of + 1/-0.8°C from - 10°C to 30°C after calibration. The sensor is embedded inside the fabricated passive UHF RFID tag. Measurement of the sensor performance at the system level is also carried out, illustrating proper sensing operation for passive RFID applications.

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This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application

In this paper, the problem of time series prediction is studied. A Bayesian procedure based on Gaussian process models using a nonstationary covariance function is proposed. Experiments proved the approach effectiveness with an excellent prediction and a good tracking. The conceptual simplicity, and good performance of Gaussian process models should make them very attractive for a wide range of problems.

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.

Gaussian process for nonstationary time series prediction

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1times0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 mum process with a silicon area of 3.1times3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements

A digital pixel sensor array with programmable dynamic range

In this paper, we describe the design, modeling, fabrication, and optical characterization of the first micropolarimeter array enabling full Stokes polarization imaging in visible spectrum. The proposed micropolarimeter is fabricated by patterning a liquid-crystal (LC) layer on top of a visible-regime metal-wire-grid polarizer (MWGP) using ultraviolet sensitive sulfonic-dye-1 as the LC photoalignment material. This arrangement enables the formation of either micrometer-scale LC polarization rotators, neutral density filters or quarter wavelength retarders. These elements are in turn exploited to acquire all components of the Stokes vector, which describes all possible polarization states of light. Reported major principal transmittance of 75% and extinction ratio of 1100 demonstrate that the MWGPs superior optical characteristics are retained. The proposed liquidcrystal micropolarimeter array can be integrated on top of a complementary metal-oxide-semiconductor (CMOS) image sensor for real-time full Stokes polarization imaging.

Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization

We fabricated and characterized a thin photo-patterned micropolarizer array for complementary metal-oxide-semiconductor (CMOS) image sensors. The proposed micropolarizer fabrication technology completely removes the need for complex selective etching. Instead, it uses the well-controlled process of ultraviolet photolithography to define micropolarizer orientation patterns on a spin-coated azo-dye-1 film. The patterned polymer film micropolarizer (10 mum x 10 mum) exhibits submicron thickness (0.3 mum) and has an extinction ratio of ~ 100. Reported experimental results validate the concept of a thin, high spatial resolution, low-cost photo-patterned micropolarizer array for CMOS image sensors.

Liquid-crystal micropolarimeter array for full Stokes polarization imaging in visible spectrum

This brief presents a CMOS temperature sensor suitable for ultralow-power applications. With a MOS transistor operating in the linear region, a linear relationship between delay and temperature can be obtained. A differential sensing architecture is utilized to reduce the signal offset and increase the effective signal-to-noise ratio. A design methodology concerning power optimization and improved sensor linearity is also presented. The sensor, which occupies 0.0324 mm2, is fabricated using the TSMC 0.18-¿m one-polysilicon six-metal (1P6M) process. Measurement results show that the sensor consumes 405 nW with a 1-V supply at 1 ksample/s at room temperature. An inaccuracy value of -0.8°C to +1°C from 0°C to 100°C after calibration is achieved.

Thin Photo-Patterned Micropolarizer Array for CMOS Image Sensors

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology

A 405-nW CMOS Temperature Sensor Based on Linear MOS Operation

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.