Amit Nahar

Quality improvement and cost reduction using statistical outlier methods

Quality improvement and cost reduction in the overall IC manufacturing and test processes are being continuously sought. Outlier screening methods can address both of these needs. As technology scales, it has become increasingly difficult to screen outliers without excessive Type I or II errors. Hundreds of parameters are collected at wafer probe, but there lacks a systematic way of selecting outlier screens. In this paper we describe a statistical approach to both identify outliers and select beneficial screening parameters more effectively. Results on a 90nm design to reduce the burn-in fails are described.

Successful Development and Implementation of Statistical Outlier Techniques on 90nm and 65nm Process Driver Devices

Burn-in and the concomitant post-burn-in retest are significant cost adders to the overall IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit analyses with parametric or non-parametric statistics, when applied to the newest technologies, result in excessive Type I or II errors which cannot be tolerated. In this paper, we describe the results from applying statistical burn-in avoidance techniques using time-zero sort test responses to driver designs fabricated in 90nm and 65nm low leakage technologies and libraries

Die-level adaptive test: Real-time test reordering and elimination

This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.

Adapting to adaptive testing

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs

We introduce a methodology for dynamically selecting whether to subject a wafer to a complete or a reduced probe-test flow, while ensuring that the concomitant test cost savings do not compromise test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. While the proposed method may offer less flexibility than approaches that dynamically adapt the test flow on a per-die basis, its implementation is simpler and more compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the dropped tests, the proposed method is capable of exploring test cost reduction solutions which maintain very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to either the complete or the reduced test flow. Training of the system seeks to maximize the number of wafers subjected to the reduced flow for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a few million devices from a Texas Instruments RF transceiver.

Multidimensional Test Escape Rate Modeling

Todays SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.

What we know after twelve years developing and deploying test data analytics solutions

Since 2004, Texas Instruments and Portland State University have collaborated to develop and deploy test data analytical methods for use in a variety of applications, including quality screening, burn-in minimization, high cost test replacement and/or removal, and operations monitoring. In this paper, key findings amassed during this time are summarized.

Harnessing fabrication process signature for predicting yield across designs

Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.

Yield prognosis for fab-to-fab product migration

We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.