Amitabh Menon

A framework for cost vs. performance tradeoffs in the design of digital signal processor cores

The TI T320C27XX DSP core is primarily targeted at the high-end control market, a typical application being the hard-disk drive. Different end-equipment segments in such a market demand varying requirements for cost and performance of the processor core. This forces certain customization in our design and design methodology to satisfy these varying requirements. A capability to perform quick cost versus performance tradeoffs in a design flow becomes imperative. This paper presents the framework used to meet this range of design requirements by controlling and constraining certain parameters that influence the cost and performance of a design.

A design methodology for a fully synthesized high speed DSP core in a deep sub-micron technology

We present a design methodology that was used to design a 150-MHz DSP core in a deep submicron technology, with emphasis on high speed and fast design cycle time. We detail the methodology, primarily based on synthesis, describe how we coupled synthesis to placement and layout and present data on our timing convergence results. We present data on experiments that we performed to tune specific steps of the methodology, which were critical to make the methodology successful.

Multivoltage scheduling with voltage-partitioned variable storage

Multivoltage scheduling (MVS) for datapaths offers the energy savings of voltage scaling on a per-operation basis with a voltage aware operator scheduling. This work investigates the effect of using multivoltage register file storage in operator graph scheduling for multivoltage datapaths, thus partitioning the variable storage space on the basis of operating voltages. Scheduling operations on multivoltage functional units lowers the energy-delay product by exploiting slack in the schedule. We find that using multivoltage partitioned register files do the same by exploiting the variable lifetimes in the schedule. In a resource constrained context, longer variable lifetimes provide the opportunity to store such variables in low voltage register files. A ZOLP formulation for the resource constrained MVS problem is presented along with energy-delay savings obtained from applying this formulation to image processing transform graphs.