Ammar Nayfeh

Thin Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells: Design and Material Quality Requirements

a-Si:H/crystalline-Si 1-x Ge x /c-Si heterojunction solar cells (HIT cells) are simulated and fabricated for the first time. Cells with junction layers consisting of Si, Si 0.75 Ge 0.25 , and Si 0.59 Ge 0.41 are compared to study the effect of increasing Ge concentration. The results show a V oc drop from 0.6V for Si cells to 0.4V for Si 0.59 Ge 0.41 , consistent with the reduction in bandgap. The measured J sc increases from ~18.5 mA/cm 2 for Si cells to 20.3 mA/cm 2 for the Si 0.59 Ge 0.41 cells, for one light pass. Simulations suggest that the measured J sc for the Si 0.59 Ge 0.41 based solar cells is limited by a low lifetime. In order for Si 1-x Ge x based cells to exceed the efficiency of Si, simulations indicate that Ge percentages larger than 40% and lifetimes above 1 ∝s are required.

Thin-Film ZnO Charge-Trapping Memory Cell Grown in a Single ALD Step

A thin-film ZnO-based single-transistor memory cell with a gate stack deposited in a single atomic layer deposition step is demonstrated. Thin-film ZnO is used as channel material and charge-trapping layer for the first time. The extracted mobility and subthreshold slope of the thin-film device are 23 cm2/V·s and 720 mV/dec, respectively. The memory effect is verified by a 2.35-V hysteresis in the Idrain- Vgate curve. Physics-based TCAD simulations show very good agreement with the experimental results providing insight to the charge-trapping physics.

Diode behavior in ultra-thin low temperature ALD grown zinc-oxide on silicon

A thin-film ZnO(n)/Si(p+) heterojunction diode is demonstrated. The thin film ZnO layer is deposited by Atomic Layer Deposition (ALD) at different temperatures on a p-type silicon substrate. Atomic force microscopy (AFM) AC-in-Air method in addition to conductive AFM (CAFM) were used for the characterization of ZnO layer and to measure the current-voltage characteristics. Forward and reverse bias n-p diode behavior with good rectification properties is achieved. The diode with ZnO grown at 80°C exhibited the highest on/off ratio with a turn-on voltage (VON) ∼3.5 V. The measured breakdown voltage (VBR) and electric field (EBR) for this diode are 5.4 V and 3.86 MV/cm, respectively.

Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission

A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ZnO steps. The threshold voltage shift (ΔVt) vs. programming voltage is studied with and without the silicon nanoparticles. Applying −1 V for 5 s at the gate of the memory with nanoparticles results in a ΔVt of 3.4 V, and the memory window can be up to 8 V with an excellent retention characteristic (>10 yr). Without nanoparticles, at −1 V programming voltage, the ΔVt is negligible. In order to get ΔVt of 3.4 V without nanoparticles, programming voltage in excess of 10 V is required. The negative voltage on the gate programs the memory indicating that holes are being trapped in the charge trapping layer. In addition, at 1 V the electric field across the 3.6 nm tunnel oxide is calculated to be 0.36 MV/cm, which is too small for significant tunneling. Moreover, the ΔVt vs. electric field acro...

Silicon-Germanium multi-quantum well photodetectors in the near infrared

Single crystal Silicon-Germanium multi-quantum well layers were epitaxially grown on silicon substrates. Very high quality films were achieved with high level of control utilizing recently developed MHAH epitaxial technique. MHAH growth technique facilitates the monolithic integration of photonic functionality such as modulators and photodetectors with low-cost silicon VLSI technology. Mesa structured p-i-n photodetectors were fabricated with low reverse leakage currents of ~10 mA/cm² and responsivity values exceeding 0.1 A/W. Moreover, the spectral responsivity of fabricated detectors can be tuned by applied voltage.

Electric-field and temperature dependence of the activation energy associated with gate induced drain leakage

We examined the effect of temperature and electric field on the activation energy (Ea) of gate-induced drain leakage (GIDL) of a MOSFET. The measured GIDL current shows a temperature dependence consistent with a non-tunneling mechanism. In the low-electric-field regime and for temperatures above 55 °C, Ea is about 0.4 eV and drops from 0.4 eV to 0.1 eV as the applied gate voltage goes below VFB in the accumulation direction (decreased for the n-channel MOSFET). This suggests that electron-hole-pair generation at Si/SiO2 interface traps (Dit), enhanced by the electric field (the Poole-Frenkel effect), dominates GIDL in that regime. For temperatures below 55 °C, Ea is less than 0.15 eV for both weak and strong electric fields and displays minimal temperature dependence, indicating inelastic trap-assisted tunneling or phonon-assisted tunneling from a trap. In the very strong-electric-field regime (>1 MV/cm), band-to-band tunneling is the dominant mechanism.

Thin film a-Si/c-Si 1−x Ge x /c-Si heterojunction solar cells with Ge content up to 56%

Thin film a-Si(n⁺)/c-Si_1-xGe_x(p)/c-Si(p⁺) heterojunction solar cells are fabricated with Ge content up to 56 atomic percent. Solar cells with junction layers consisting of Si, Si_0.75Ge_0.25, Si_0.59Ge_0.41, and Si_0.44Ge_0.56 are compared to study the effect of increasing Ge concentration. The measured short-circuit current (J_sc) increases from ~14 mA/cm² for Si cells to 21 mA/cm² for the Si_0.44Ge_0.56 cells, for one light pass and a 2 μm-thick SiGe layer. The results show an open-circuit voltage (V_oc) of 0.61 V for Si cells, dropping to 0.32 V for Si_0.44Ge_0.56, consistent with the reduction in band-gap. Quantum efficiency measurements highlight the improved spectral response for higher Ge percentages. Physics based TCAD simulations combined with the experimental results are used to extract lifetime and interface velocity.

Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer

In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-Vgate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (Vt) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the Vt shift direction indicates that electrons tunnel from channel to charge storage layer.

Enhanced memory effect with embedded graphene nanoplatelets in ZnO charge trapping layer

A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) is demonstrated. The memory shows a large threshold voltage Vt shift (4 V) at low operating voltage (6/−6 V), good retention (>10 yr), and good endurance characteristic (>104 cycles). This memory performance is compared to control devices with graphene nanoplatelets (or ZnO) and a thicker tunnel oxide. These structures showed a reduced Vt shift and retention characteristic. The GNIZ structure allows for scaling down the tunnel oxide thickness along with improving the memory window and retention of data. The larger Vt shift indicates that the ZnO adds available trap states and enhances the emission and retention of charges. The charge emission mechanism in the memory structures with graphene nanoplatelets at an electric field E ≥ 5.57 MV/cm is found to be based on Fowler-Nordheim tunneling. The fabrication of this memory device is compatible with current semiconductor processing, therefore, has great potentia...

Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer

A functional zinc-oxide based SONOS memory cell with ultra-thin chromium oxide trapping layer was fabricated. A 5 nm CrO2 layer is deposited between Atomic Layer Deposition (ALD) steps. A threshold voltage (Vt) shift of 2.6V was achieved with a 10V programming voltage. Also for a 2V Vt shift, the memory with CrO2 layer has a low programming voltage of 7.2V. Moreover, the deep trapping levels in CrO2 layer allows for additional scaling of the tunnel oxide due to an increase in the retention time. In addition, the structure was simulated using Physics Based TCAD. The results of the simulation fit very well with the experimental results providing an understanding of the charge trapping and tunneling physics.