Anand Ramalingam

Sleep transistor sizing using timing criticality and temporal currents

Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to gate the power supply. This paper presents a new methodology based on timing criticality and temporal currents to size the sleep transistor. The timing criticality information and temporal current estimation are obtained using static timing analyzer. The results obtained indicate that our proposed technique results in area reduction of sleep transistors by 80% and 49% compared to module based design and cluster based design respectively.

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce

Power gating is a very effective technique to reduce the subthreshold leakage by using sleep transistors to turn off the functional blocks or cells when they are not used. When the sleep transistors are turned on, the power grid may experience a huge current surge which may violate the integrity of the power grid. This paper addresses this problem by formulating the wakeup scheduling of sleep transistors as an exact mixed integer linear program (MILP). Since the resulting MILP is hard, we propose a very efficient yet near optimal algorithm by successively relaxing the MILP to a sequence of linear program (LP) problems. The results obtained on the ISCAS benchmarks indicate that our proposed algorithm obtains a near optimal solution with a speedup of 15× on average compared to the MILP. The proposed algorithm has a runtime complexity which is linear in practice.

Accurate waveform modeling using singular value decomposition with applications to timing analysis

It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a flexible trade-off of accuracy vs. computational and representational cost. The technique is based on singular value decomposition (SVD) and it naturally leads to a more general gate delay model which can be applied in any timing analysis engine with minor modifications. We demonstrate its application in timing analysis by propagating a waveform along a path. When compared with Spice, the proposed model shows good accuracy.

Robust analytical gate delay modeling for low voltage circuits

Sakurai-Newton (SN) delay metric (Sakurai, 1990) is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that the SN metric fails to provide high accuracy and fidelity when CMOS gates operate at low supply voltages. Thus it may not be applicable in many low power applications with voltage scaling. In this paper, we propose a new closed form delay metric based on the centroid of power dissipation. This new metric is inspired by our key observation and theoretic proof that the SN delay is indeed Elmore delay, which can be viewed as the centroid of current. Our proposed metric has a very high correlation coefficient (ges 0.98) when correlated with the actual delays got from the HSPICE simulations. Such high correlation is consistent across all major process technologies. In comparison, the SN metric has a correlation coefficient between (0.70, 0.90) depending upon the technology and the CMOS gate, and it is less accurate for lower supply voltages. Since our proposed metric has high fidelity across a wide range of supply voltages yet a simple closed form, it is very useful to guide low voltage and low power designs

Latch modeling for statistical timing analysis

Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new latch delay model in the context of SSTA based on a new perspective of latch timing. The proposed latch model also takes into account the external timing variations such as data slew. The new latch model is integrated into SSTA by considering the timing analysis of both the combinational logic network and the clock distribution network simultaneously. The experimental results show that ignoring accurate latch modeling may lead to large errors (e.g., 50% at PDF peak).

Accurate power grid analysis with behavioral transistor network modeling

In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for power grid analysis rely on a model of representing the transistor network as a current source. The disadvantage of the above model is that the drain capacitance of the PMOS transistors which are already on is not modeled. The drain capacitance of the PMOS transistors which are on, act much like a decoupling capacitance in the power grid. By ignoring the drain capacitance, the voltage drop predicted is pessimistic. This implies that a designer is likely to overestimate the amount of decoupling capacitance needed. In our proposed model, we model the transistor network as a simple switch in series with a RC circuit. The presence of switches leads to a non-constant conductance matrix. So, the switch is modeled behaviorally to make the conductance matrix a constant in presence of switches. The resulting conductance matrix is a M-matrix thus making it amenable to linear algebraic methods presented in the literature. The proposed model is nearly as accurate as the SPICE model in predicting the voltage drop. We demonstrate that the current source model of the transistor network has an error of about 10% in predicting the voltage drop. The proposed model offers the middle ground between the accuracy of SPICE simulation and the speed of the current source model. The proposed model is 20--30x faster than SPICE. It also reduces the size of the decoupling capacitance by 2--10x in comparison with the methods presented in the literature.

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity

The increase in packing density has led to a higher power density in the chip which in turn has led to an increase in temperature on the chip. Temperature affects reliability, performance and power directly, motivating the need to accurately simulate the thermal profile of a chip. In literature, thermal conductivity is assumed to be a constant in order to obtain a linear system of equations which can be solved efficiently. But thermal conductivity is a nonlinear function of temperature and for silicon it varies by 22% over the range 27-80deg C (McConnell et al., 2001). If the nonlinearity of the thermal conductivity is ignored the thermal profile might be off by 10deg C. Thus to get an accurate thermal profile it is important to consider the nonlinear dependence of the thermal conductivity on temperature. In this work the nonlinear system arising out of considering the nonlinear thermal conductivity is solved efficiently using a variant of Newton-Raphson. We also study the abstraction levels under which the approximation of a periodic source by a DC source is valid