Anant Deval
Intel
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Publication
Featured researches published by Anant Deval.
international solid-state circuits conference | 2014
Nasser A. Kurd; Muntaquim Chowdhury; Edward A. Burton; Thomas P. Thomas; Christopher P. Mozak; Brent R. Boswell; Manoj B. Lal; Anant Deval; Jonathan P. Douglas; Mahmoud Elassal; Ankireddy Nalamalpu; Timothy M. Wilson; Matthew C. Merten; Srinivas Chennupaty; Wilfred Gomes; Rajesh Kumar
The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary goals for the Haswell program are platform integration and low power to enable smaller form factors. Haswell incorporates several building blocks, including: platform controller hubs (PCHs), memory, CPU, graphics and media processing engines, thus creating a portfolio of product segments from fan-less Ultrabooks™ to high-performance desktop, as shown in Fig. 5.9.1. It also integrates a number of new technologies: a fully integrated voltage regulator (VR) consolidating 5 platform VRs down to 1, on-die eDRAM cache for improved graphics performance, lower-power states, optimized IO interfaces, an Intel AVX2 instruction set that supports floating-point multiply-add (FMA), and 256b SIMD integer achieving 2× the number of floating-point and integer operations over its predecessor. The 22nm process is optimized for Haswell and includes 11 metal layers (2 additional metal layers vs. Ivy Bridge [2]), high-density metal-insulator-metal (MIM) capacitors, and is tuned for different leakage/speed targets based on the market segment. For example, in some low-power products, the process is optimized to reduce leakage by 75% at Vmin, while paying only 12% intrinsic device degradation at the high-voltage corner.
IEEE Journal of Solid-state Circuits | 2015
Nasser A. Kurd; Muntaquim Chowdhury; Edward A. Burton; Thomas P. Thomas; Christopher P. Mozak; Brent R. Boswell; Praveen Mosalikanti; Mark Neidengard; Anant Deval; Ashish Khanna; Nasirul Chowdhury; Ravi Rajwar; Timothy M. Wilson; Rajesh Kumar
We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”) implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( ~ 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.
symposium on vlsi circuits | 2015
Ankireddy Nalamalpu; Nasser A. Kurd; Anant Deval; Christopher P. Mozak; Jonathan P. Douglas; Ashish Khanna; Fabrice Paillet; Gerhard Schrom; Boyd S. Phelps
Intel Core™ M and 5th generation of Core™ processors (code named Broadwell) are fabricated on an optimized 14 nm process technology node resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core™ M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up-to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 m V. Broadwell introduces the second generation of Fully Integrated Voltage Regulator with better droop control and parallel boot LVR along with other power-reduction features resulting in 35% reduction in active and standby power over first generation. 3DL inductor technology introduced for the first time in Broadwell, enables 30 % reduction in package thickness and improved low-load efficiency. IO re-partitioning of the SOC and a major re-design of DDR system resulted in 30% reduction in I/O power. Shutting down various parts of the SOC die in various idle states (C* states) resulted in 60% reduction in the idle power. New software controlled co-optimization methods were implemented such as duty-cycle control and dynamic display support to improve the energy efficiency of the graphics and the display subsystem.
2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII) | 2015
Anant Deval; Avinash N. Ananthakrishnan; Craig Forbell
The desire to deliver breakthrough performance in a tablet form factor required several innovations in the 14nm Intel® flagship Core™ processor (Broadwell). Better frequency control algorithms including duty cycling graphics cores were developed to improve energy efficiency. New power sharing algorithms were developed to maximize performance of multiple compute domains within tight thermal and power delivery constraints. Innovations resulted in upto 50% increase in performance and upto 25% improvement in battery life over a Haswell system thermally constrained to a 4.5W fanless form factor.
Archive | 2012
Stephen H. Gunther; Edward A. Burton; Anant Deval; Stephan J. Jourdan; Robert J. Greiner; Michael P. Cornaby
Archive | 2010
Edward A. Burton; Robert J. Greiner; Anant Deval; Douglas R. Huard; Jeremy J. Shrall; Arun R. Ramadorai; Benson D. Inkley; Martin M. Chang
Archive | 2005
Edward A. Burton; Anant Deval; Nivruti Rai
Archive | 2006
Stephen H. Gunther; Edward A. Burton; Anant Deval; Stephan J. Jourdan; Robert J. Greiner; Mike Cornaby
Archive | 2006
Edward A. Burton; Robert J. Greiner; Anant Deval; Douglas R. Huard
Archive | 2006
Edward A. Burton; Robert J. Greiner; Anant Deval; Doug Huard; David Perchlik