András Timár

Temperature dependent timing in standard cell designs

This paper proposes a methodology to simulate temperature dependent timing in standard cell designs. Temperature dependent timing characteristics are derived from standard delay format (SDF) files that are created by synthesis tools automatically. A case study is also presented in this paper where the temperature dependent frequency variation of a ring oscillator is simulated demonstrating the necessity of temperature dependent timing simulations. An adaptively refineable partitioning method for simulating standard cell designs logi-thermally is proposed as well. This paper also introduces recent enhancements in the CellTherm logi-thermal simulator developed in the Department of Electron Devices, BME, Hungary.

Design issues of a low frequency low-pass filter for medical applications using CMOS technology

In the past few decades, medical and biological researches gained more and more attention. The ever-growing need for such researches caused many medical applications to develop. Collecting data from a living human body is a complex task and needs circumspection. In this paper, specific issues of the most important part of such a data acquisition system is presented, the design of a low pass filter. The major issue to overcome in the design of a system that is aimed at being built into the human body is creating large value capacitances needed to the realization of filters for the specific application. After presenting the special requirements for low pass filters for medical applications the method of creating large capacitors is presented in details in the paper.

Real-time heating and power characterization of cells in standard cell designs

In todays digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell ICs surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each consisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the ICs surface. This paper also presents various aspects of power characterization methods which were used throughout the experiments.

Logi-thermal simulation using high-resolution temperature dependent delay models

This paper proposes an accurate temperature dependent delay model for logi-thermal simulations. During the logi-thermal simulation of digital integrated circuits the propagation delays of the standard cells can be calculated from delay-temperature functions. The delay-temperature functions contain exact and precise delay values for each input-output path and temperature value. Temperature characterization corners can be specified in arbitrary fine granularity and range. The model presented in this paper overcome the limitation of the classic SDF (Standard Delay Format) models in that propagation delay values can be given for arbitrary temperatures, not only a few corners. With classic SDF, temperature dependence of timing and thus power can only be taken into account for a few design corners. Between characterization corners, like supply voltage, process variation and temperature, linear interpolation must be used for intermediate data. With our proposed delay model temperature-aware timing simulations would produce more accurate results than the classic SDF model. This paper compares the classic SDF delay model with our temperature dependent detailed model and provides evidence through a simple example for the necessity of temperature-aware timing simulation. The logi-thermal simulations are carried out with the CellTherm[1] application developed in the Dept. of Electron Devices, BME, Hungary. A logi-thermal acceleration technique is also introduced in this paper.

New simulation approaches supporting temperature-aware design of digital ICs

Regarding thermal issues in digital IC design a major concern is how timing integrity is affected by the elevated junction temperature and temperature gradients on the chip surface. To predict this in a thermal aware design process one needs a dedicated simulation tool in which the logic simulation of the circuit is coupled to the thermal simulation of the chip and its environment. This paper presents two approaches to this so called logithermal simulation. In one of our approaches we rely completely on industry standard EDA tools, standard EDA file formats and interfaces. In the other solution which provides us total freedom in the abstraction level of circuit description and simulation accuracy we use our own logic simulation engine. In both cases the logic simulation engine is connected to our own thermal simulation engines which also use compact thermal models of the IC package during simulation. This paper describes certain implementation aspects and features of our logithermal simulation solutions, with emphasizes on modeling the thermal properties of the IC packaging.

Smart SSL: Application of IoT/CPS design platforms in LED-based street-lighting luminaires

Smart systems - according to a simplistic definition - provide new qualities and new functionalities through the integration of formerly distinct functions, components and networks. Street-lighting (as other lighting applications) recently went already through a drastic change offered by “LEDification”. The easy electronic controllability of LEDs as light sources triggered a new change of paradigm: integration of LED based luminaires into smart systems. Smart integration necessitates among others both adaptability to the environmental conditions and intelligent remote control that require a communications systems based on a multi-layer data transfer protocol. We are reporting about an ongoing project that targets a “future proof” solution which is not restricted to lighting control but allows public lighting installations to play key roles in other smart city functions needed in outdoor public spaces such as communications with vehicles. The result of the development is a new IoT device which can be installed in street-lighting luminaires and allows physical layer (e.g. PLC, WiFi, ZigBee or other RF transmission) independent data transfer. The main functionality of the application layer of the protocol remains of course lighting control which is best implemented on the basis of existing standards (such as DALI), but the system allows the implementation of other communications tasks based on other application layer protocols.

Acquiring real-time heating of cells in standard cell designs

In todays digital electronic integrated circuits device heating is one of the most critical issues. Overheating can cause failures in functionality and device malfunction. In certain circumstances overheating of ICs can cause physical destruction of the device itself. This paper introduces a solution to determine cell and gate heating curves across the standard cell ICs surface. The presented methodology and toolset is tightly integrated into standardized logic simulator engines thus providing digital circuit designers a low-level, cell-resolution temperature distribution map during logic simulations. Actual temperatures of each con- sisting cell of the design can be monitored throughout the whole logic simulation. By being able to monitor temperatures of digital cells during initial simulations, it allows us to detect hot-spots and overheating caused malfunctions far before manufacture. By using the spatial location and temperature magnitude of hot-spots acquired from the presented methodology, place and route (P&R) tools can be driven to change cell placement and routing in order to avoid heating caused failures. Additionally, cooling solutions can be developed using the simulated temperature maps of the ICs surface.

Contactless characterization of MEMS devices using optical microscopy

In this paper a new approach for measuring depth values of cavities of Micro-Electro Mechanical System (MEMS) is presented. This measurement was done by using a simple optical microscope and image processing techniques. The sample need not to be treated with any foreign material such as reflective or conductive coating.