Andre Heilper

Performance analysis and visualization tools for cell/B.E. multicore environment

Code porting, optimizing and tuning has become a challenging task in multicore/many cores environment. It requires a different set of performance visualization tools to handle the complexity of the many cores and the size of performance data to find opportunities for optimization. This paper discusses performance visualization tools available for Cell/B.E. under the IBM Software Development Kit (SDK) for Multicore Acceleration Version 3.0. It also presents a methodology for porting, optimizing and tuning Cell applications by utilizing those tools. The paper starts with a simple scalar program example which can also be found in the IBM tutorial for the Cell programming, and then describes all the needed steps to make it fully tuned and scaled for the Cell Broadband Engine.

Retail applications of signature verification

The dramatic rise in identity theft, the ever pressing need to provide convenience in checkout services to attract and retain loyal customers, and the growing use of multi-function signature captures devices in the retail sector provides favorable conditions for the deployment of dynamic signature verification (DSV) in retail settings. We report on the development of a DSV system to meet the needs of the retail sector. We currently have a database of approximately 10,000 signatures collected from 600 subjects and forgers. Previous work at IBM on DSV has been merged and extended to achieve robust performance on pen position data available from commercial point of sale hardware, achieving equal error rates on skilled forgeries and authentic signatures of 1.5% to 4%.

Cell broadband engine processor performance optimization: tracing tools implementation and use

Optimizing performance on multicore processors is a daunting task M. S. Chang because of the increased importance of such factors as thread communication, memory contention, and memory access latency. This paper presents two tools that programmers and performance analysts can use to understand application performance on the Cell Broadband Engine® (Cell/B.E.) processor: the Performance Debugging Tool (PDT) and the Trace Analyzer (TA). PDT traces user-space events, augmenting them with scheduling data from the operating system; those traces are then read, analyzed, and presented visually by the TA. This paper describes the implementation issues arising from the fact that a common lowoverhead clock shared by all cores, essential for analysis and visualization, is not available on the Cell/B.E. processor. The TA employs an offline analysis to align the collected events to a common time based only on thread-local timestamps, event order, and context switch information. We also discuss the overhead of tracing and its impact on execution and performance analysis. We illustrate the use of the PDT and TA by analyzing several significant Cell/B.E. processor workloads, including native code and higher-level abstractions offered by the Data Communication and Synchronization services. We show how trace analysis can help identify performance issues in these workloads and how it can be used by programmers to spot performance antipatterns (common programming practices leading to suboptimal performance).