Andrea Bonfanti

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/.

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.

Phase noise and accuracy in quadrature oscillators

This paper proposes a complete analysis of quadrature-coupled LC oscillators. These oscillators operate off-resonance and for this reason, their phase noise worsens at increasing coupling strength. Since the coupling transistors raise the total power consumption, the noise-power product degrades further with respect to a stand-alone oscillator. On the other hand, at high coupling factors component mismatches affect less the phase accuracy of the quadrature outputs. Closed-form expressions for phase noise and phase accuracy are derived which are verified against circuit simulations.

A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs

Amplitude-to-phase-noise conversion due to varactors can severely limit the close-in phase noise performance in LC-tuned oscillators. This work proposes a rigorous analysis of this phenomenon, which highlights the fundamental limitations of single-ended tuned and differentially tuned diode varactor configurations. The back-to-back varactor topology is identified as a suitable solution to linearize the tank capacitance. The amplitude to phase noise conversion is greatly attenuated and the 1/f3 phase noise is drastically reduced, without impairing the achievable tuning range. These results are validated through circuit simulations in an existing 0.35-mum CMOS technology

A 15-GHz broad-band /spl divide/2 frequency divider in 0.13-/spl mu/m CMOS for quadrature generation

This letter presents a 0.13-/spl mu/m CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of the loop gain phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15GHz, featuring a 31% locking range. The divider dissipates 3mA from a 1.2-V power supply.

General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the single sideband to carrier ratio (SSCR). The validity of the relationship between the time- and frequency-domain figures of merit has been first tested through the simulation of a widely popular case: the phase noise spectrum featured by PLL synthesizers. As a further proof, measurements have also been performed on CMOS and bipolar integrated VCOs and PLLs, by adopting time-to-amplitude conversion techniques.

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators

Harmonic content modulation of the oscillator output voltage can contribute to flicker noise up-conversion in LC-tuned oscillators. The paper reports a quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF). It is shown that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform, and from the first harmonic of the transistor current, which is slightly lagging the voltage waveform. A closed-form expression of 1/f3 phase noise in voltage-limited LC-tuned oscillator is derived that is in good agreement with circuit simulations. The paper also shows that the values of both phase shifts are determined by the non-linearity of the active element and are linked to the relevant oscillator parameters, i.e., excess gain and tank quality factor.

A DDS-based PLL for 2.4-GHz frequency synthesis

In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 /spl mu/s for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9/spl deg/ rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.

A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission

This paper reports a multi-channel neural spike recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit (16 active channels plus 48 ”mute” lines) demonstrates the potentials of a 64-channel system made by a low-noise analog front-end, a single 8-bit SAR ADC, followed by digital signal compression and transmission units. The 400-MHz transmitter uses a Manchester-Coded Frequency Shift Keying (MC-FSK) with low modulation index. In this way a 1.25-Mbit/s data rate is delivered within a band of about 3MHz. Compression of the raw data is implemented by detecting the action potential (AP) spikes and storing up to 20 points for each waveform. The choice greatly improves data quality and allows single spike identification. The chip, fabricated in 0.35-µm CMOS AMS process, occupies a 3.1 × 2.7 mm2 area. A 4-m transmission range is reached with an overall power consumption of 16.6 mW. The figure translates into a power budget of 269 µW per channel for a complete 64-channel system, which favorably compares with the results in literature. The system performance has been verified in in-vivo neural recording experiments.

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant network [1], (ii) reduction of transistor size [2] or (iii) insertion of source degeneration [3]. However, resonant solutions do not guarantee suppression over a wide frequency range, while the other options affect the oscillator start-up margin and degrade the “white” 1/f2 phase noise. This work presents an alternative technique that does not rely on resonant elements and does not affect both start-up margin and 1/f2 phase noise. Demonstration of the technique is described in a 65nm CMOS VCO design.