Andrea Marmiroli

Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices

The magnitude of a random telegraph signal (RTS) in nanoscale floating-gate devices has been experimentally investigated as a function of carrier concentration. Discrete current switching, which is caused by a single trap, has been found to be almost one order of magnitude higher with respect to what was predicted by the classical theory of carrier number and correlated mobility fluctuations. Nevertheless, the trap signature well fits the typical SiO2 trap spectroscopy. In addition, the rigid shift between the transfer curves related to filled- and empty-trap state, together with the normalized current fluctuation dependence on the channel carrier density, suggests that a pure number fluctuation is the correct theoretical interpretative framework. Thus, we propose a possible physical explanation for such a giant RTS on the basis of a quasi-1-D current filamentation.

A new compact DC model of floating gate memory cells without capacitive coupling coefficients

This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively the complete DC electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on E/sup 2/PROM and flash memory cells manufactured in existing technology (0.35 /spl mu/m and 0.25 /spl mu/m) by STMicroelectronics.

Influence of the silicon nitride oxidation on the performances of NCLAD isolation

A Deal and Grove model for the oxidation of the nitride isolation masks has been found, and has been implemented in the 2D Process simulator IMPACT-4 [2]. This implementation permitted to study the effects of this oxidation on the performances of NCLAD LOCOS/Recessed-LOCOS isolation structures.

Technology and Device Modeling in Micro and Nano-electronics: Current and Future Challenges

The number of physical effects that have to be taken into account to accurately model and design current and future micro- and nano-electronics devices is continuously increasing. At the same time, the importance of the coupling among them is increasing as well. An accurate simulation of such effects with strong interactions is often non-trivial and in many cases a satisfactory solution is not yet available. Two challenging problems are presented in more detail: the first one refers to the thermomechanical problem of silicon oxidation, the second is the electrical coupling which occurs in strained silicon substrate.

A New Compact Spice-like Model of E2PROM Memory Cells Suitable for DC and Transient Simulations

This paper presents for the first time a new compact Spice-like model of a E2PROM Memory Cells suitable for both DC and transient circuit simulations. This model is based on a new Floating Gate voltage calculation procedure that improves strongly the accuracy of the modeling of the cell. Moreover, this model features many advantages compared to the previous ones: i) it is simple to implement and scale; ii) its computational time is not critical; iii) its parameter extraction procedure is the same of a MOS transistor; iv) it can be easily upgraded to take into account leakage current contributions (SILC).

Optimization of a Recessed LOCOS using a tuned 2-D process simulator

The application of the conventional LOCOS technique (LOCal Oxidation of Silicon) to grow oxide structures for IC device isolation is no longer effective below 0.5 µm. In order to support the optimization of an alternative isolation technique, adequate simulations tools arc required. In this work we describe an accurate tuning of 2-D simulation program, which uses a viscoclastic model for the oxidation of silicon, and its application to the optimization Recessed LOCOS isolation.