Andreas Antoniou

Area-efficient multipliers for digital signal processing applications

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncated multiplier, is described. The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but in order to keep the quantization error to a minimum, probabilistic biases are obtained and are then fed to the inputs of the retained adder cells. The truncated multiplier requires approximately 50% of the area of a standard parallel multiplier. The paper then shows that this design strategy can also be applied for the design of twos-complement multipliers. The paper concludes with the application of the truncated multiplier for the implementation of a digital filter and it is shown that the signal-to-noise ratio of the digital filter using a truncated multiplier is better than that using a standard multiplier.

A New Peak-to-Average Power-Ratio Reduction Algorithm for OFDM Systems via Constellation Extension

Peak-to-average power-ratio (PAPR) reduction for OFDM systems is investigated in a probabilistic framework. A new constellation extension technique is developed whereby the data for each subcarrier are represented either by points in the original constellation or by extended points. An optimal representation of the OFDM signal is achieved by using a de-randomization algorithm where the conditional probability involved is handled by using the Chernoff bound and the evaluation of the many hyperbolic cosine functions involved is replaced by a tight upper bound for these functions. The proposed algorithm can be used by itself or be combined with a selective rotation technique described in the paper and with other known algorithms such as the coordinate descent optimization and selective mapping algorithms to achieve further performance enhancements at the cost of a slight increase in the computational complexity. When compared with other existing PAPR-reduction algorithms, the enhanced algorithm offers improved PAPR-reduction performance and improved computational complexity although, the transmit power is increased somewhat

Synthesis of 2-D state-space fixed-point digital-filter structures with minimum roundoff noise

Based on a roundoff-noise analysis, a general synthesis procedure is developed which leads to an optimal local state-space 2-D digital-filter realization that minimizes the output-noise power due to roundoff subject to a scaling condition on the state variables. The outputnoise power and the signal scaling condition are closely related to two positive-definite matrices W and K . These matrices provide two sets of invariants, called the 2-D second-order modes of the filter, which play a crucial role in the minimization of the output-noise power. With the availability of matrices W and K , the 2-D similarity transformation that yields an optimal state-space realization can be obtained by solving separately two 1-D optimization problems so that the well-developed techniques for minimizing roundoff noise in 1-D state-space digital filters can also be used for minimizing roundoff noise in 2-D state-space digital filters.

Low power dissipation MOS ternary logic family

An MOS ternary-logic family comprising a set of inverters, NOR gates, and NAND gates is proposed. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other known ternary circuits; these include low power dissipation and reduced propagation delay and component count. For a given dynamic range, the complexity of the new ternary circuits is shown to be comparable to that of corresponding binary circuits. Nevertheless, the associated reduction in the wordlength in the case of the ternary circuits tends to alleviate to a large extent the pin limitation problem associated with VLSI implementation. The authors conclude with an implementation of the cyclic convolution, an application in which a significant advantage can be gained through the use of ternary digital hardware.

Efficient iterative design method for cosine-modulated QMF banks

An iterative algorithm for the design of multichannel cosine-modulated quadrature mirror-image filter (QMF) banks with near-perfect reconstruction is proposed. The objective function is formulated as a quadratic function in each step whose minimum point can be obtained using a closed-form solution. This approach has high design efficiency and leads to filter banks with high stopband attenuation and low aliasing and amplitude distortions. The proposed approach is then extended to the design of multichannel cosine-modulated QMF banks with low reconstruction delays, which are often required, especially in real-time applications. Several design examples are included to demonstrate the proposed algorithms, and some comparisons are made with existing designs.

Design of ultraspherical window functions with prescribed spectral characteristics

A method for the design of ultraspherical window functions that achieves prescribed spectral characteristics is proposed. The method comprises a collection of techniques that can be used to determine the three independent parameters of the ultraspherical window such that a specified ripple ratio and main-lobe width or null-to-null width along with a user-defined side-lobe pattern can be achieved. Other known two-parameter windows can achieve a specified ripple ratio and main-lobe width; however, their side-lobe pattern cannot be controlled as in the proposed method. A comparison with other windows has shown that a difference in performance exists between the ultraspherical and Kaiser windows, which depends critically on the required specifications. The paper also highlights some applications of the proposed method in the areas of digital beamforming and image processing.

A generalized Remez method for the design of FIR digital filters

A generalized Remez method for the design of finite impulse response (FIR) filters is proposed. The method is based on a new problem formulation which largely eliminates certain difficulties brought about by an undetermined approximating polynomial. The new method can be used to design maximal-ripple (MR), extra-ripple (ER), and weighted-Chebyshev filters satisfying prescribed specifications, and, with the addition of some simple techniques, filters can be designed that are free from transition region anomalies. The method incorporates a new initialization strategy and a selective search technique to reduce the amount of computation needed to carry out a design. Extensive experimental results show that the new method is robust and at least as efficient as existing methods for the design of weighted-Chebyshev filters. For MR as well as ER filters, the new method is both robust and very efficient. >

A new DOA estimation technique based on subarray beamforming

A new direction-of-arrival (DOA) estimation technique using subarray beamforming is proposed. Two virtual subarrays are used to form a signal whose phase relative to the reference signal is a function of the DOA. The DOA is then estimated based on the computation of the phase shift between the reference signal and its phase-shifted version. Since the phase-shifted reference signal is obtained after interference rejection through beamforming, the effect of cochannel interference on the estimation is significantly reduced. The proposed technique is computationally simple, and the number of signal sources detectable is not bounded by the number of antenna elements used. Performance analysis and extensive simulations show that the proposed technique offers significantly improved estimation resolution, capacity, and accuracy relative to existing techniques

Novel RC-active-network synthesis using generalized- immittance converters

A general synthesis procedure capable of realizing any stable transfer function is described; generalized-immittance converters are used in which the input immittance is proportional to s^{2} \times load immittance. The resulting realizations are shown to have low sensitivity to element variations. The sensitivity in realizations of second-order transfer functions is independent of the selectivity and it is shown to be much lower than the sensitivity in realizations using positive-gain amplifiers or negative-immittance converters. A unique feature is that in some cases the same circuit can be used as a low-pass as well as a high-pass filter. The synthesis procedure is illustrated by examples and experimental results.

A Family of Shrinkage Adaptive-Filtering Algorithms

A family of adaptive-filtering algorithms that uses a variable step size is proposed. A variable step size is obtained by minimizing the energy of the noise-free a posteriori error signal which is obtained by using a known