Andreas Kohler

z/CECSIM: an efficient and comprehensive microcode simulator for the IBM eServer z900

An IBM eServer zSeries™ system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE). Each microcode component must be verified by itself and in conjunction with the others. Tight development schedules and a very limited supply of expensive engineering hardware make it desirable to perform this verification in a simulation environment. For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented. Several microcode components are connected in a single simulation environment, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware. z/CECSIM creates a virtual zSeries CEC on VM/ESA® or z/VM™ that allows the simulation of zSeries microcode. It executes the instruction stream as completely as possible on the underlying hardware. Only instructions that are newly introduced with the system being developed or that perform a microcode-internal function are simulated. Additional software models mimic the behavior of I/O and coupling channels. An optional SE connection allows verification of interactions between the CEC and its support element.

IBM system z10 firmware simulation

While a number of techniques to further improve firmware quality H. Elfering and design stability and to reduce firmware field problems over the long term were introduced with the IBM z900 and z990, a second wave of techniques were introduced for the IBM System z10™ platform. This paper describes the three new techniques: an enhanced static code analysis tool, code coverage, and simulation improvements.

Advanced firmware verification using a code simulator for the IBM System z9

Our methods for simulating host firmware of the IBM System z9TM facilitated rapid development From first power-on of the system to achieving a platform with a functional operating system. Hundreds of code bugs were eliminated before the code was run on System z9 hardware for the first time. This paper describes the methods used in host firmware simulation for early and efficient firmware tests. The central element for firmware simulation is the Central Electronic Complex Simulator (CECSIM), which offers new facilities to manage the hardware of the simulated system. This management includes concurrent configuration changes of processors, memory, and I/O along with the ability to automatically test complex system functions. To verify correct implementation of the z/ArchitectureTM, we introduced a new test-case framework called the Verification Interface for System Architecture, or VISA, which is used in simulations as well as on the actual system. All of these features are used separately and in combination. A comprehensive and flexible regression environment ensures periodic execution of the test scenarios, and code path coverage measurements show the degree to which the code was actually verified.

IBM Parallel Sysplex design for the IBM z196 system

The coupling adapter hub of an IBM System z® server is a key component for the IBM System z Parallel Sysplex®. The hub is built to exchange messages between systems in a highly efficient manner. This paper describes the latest generation of high-fanout and low-latency coupling adapter cards, the associated firmware, and a new protocol. As in the z10® system, there is a long-range and a short-distance card. The coupling adapter for zEnterprise® 196 (z196) is based on the z10 infrastructure (InfiniBand® link layer), with the internal transport engine for message handling completely redesigned to support the new protocol and improve connectivity, latency, and throughput. In addition to enabling the new adapters functionality, the Parallel Sysplex support firmware has several significant enhancements in a number of functional areas. Connectivity and utilization are improved through the ability to define more channels and more concurrent connections (message buffer sets) for each channel. Through a combination of hardware and firmware protocols, response time for messages at a short distance is significantly improved. Finally, new methods are presented that support efficient presilicon and postsilicon functional and performance verification.

Enhanced I/O subsystem recovery and availability on the IBM System z9

Although part of the IBM System zTM strategy is to improve design and development processes to prevent errors from escaping to the field, improving recovery is another element in the strategy to keep a machine up and running should an error occur. The z9TM continues on an evolutionary path of enhancing I/O subsystem (IOSS) recovery to further advance the reliability, availability, and serviceability (RAS) of System z platforms. This paper presents an overview of recovery and how it interacts with other RAS functions--such as error-detection mechanisms in hardware, including automatic identification and recovery of failing elements--up to the point in time prior to the advent of the z9. It then presents the innovations to IOSS recovery and error detection in the z9 that further improve machine availability. The recovery infrastructure, which significantly reduces recovery time and makes recovery much less dependent on machine scaling for this and future generations of System z servers, is described. Also described are such innovative uses of this new infrastructure as improvements in error detection related to elusive firmware problems seen in prior machines, the ability to detect and recover from firmware hangs or lockups related to inadvertently leaving control blocks locked, and the capability to perform recovery in parallel by multiple system-assist processors.