Andreas Svolos

Efficient binary morphological algorithms on a massively parallel processor

One of the most important features in image analysis and understanding is shape. Mathematical morphology is the image processing branch that deals with shape analysis. The definition of all morphological transformations is based on two primitive operations, i.e. dilation and erosion. Since many applications require the solution of morphological problems in real time, researching time efficient algorithms for these two operations is crucial. In this paper efficient parallel algorithms for the binary dilation and erosion are presented and evaluated for an advanced associative processor. Simulation results indicate that the achieved speedup is linear.

Efficient parallel algorithm for hierarchical block-matching motion estimation

Motion estimation is an integral part of most of the video coding schemes that have been proposed in the literature. It is also the most computationally intensive part in these schemes and thus is usually implemented on high performance parallel architectures. In this paper, we deal with a multiresolution (hierarchical) block matching motion estimation algorithm. Specifically, we parallelize this algorithm on a hypercube based multiprocessor. As this algorithm presents a non regular data flow, it could not be easily implemented on systolic arrays. In contrast, the use of such an advanced network as the hypercube overcomes the problem of the non regular data flow, thereby providing high performance. Another important point in our study is that our multiprocessor is assumed to be fine grained unlike most of multiprocessors that has been proposed for video coding schemes. The constraint of limited local memory in each processor leads to frequent interprocessor communication and thus the employed techniques should be carefully selected in order to lower the communication overhead. Coarse grained architectures do not have this kind of problem because each processor can take most of the data it will need throughout the algorithm execution from the beginning. This greatly reduces the communication overhead, and thus the algorithm design is rather straightforward in this case.

Efficient binary and grey level morphological operations on a massively parallel processor

One of the most important features in image analysis and understanding is shape. Mathematical morphology is the image processing branch that deals with shape analysis. The definition of all morphological transformations is based on two primitive operations, i.e. dilation and erosion. Since many applications require the solution of morphological problems in real time, researching time efficient algorithms for these two operations is crucial. †The implementation of the above functions is beyond the scope of this paper. In this paper, efficient algorithms for the binary as well as the grey level dilation and erosion are presented and evaluated for an advanced associative processor. It is shown through simulation results that the above architecture is near optimal in the binary case and is also as efficient as the array processor with a 2D-mesh interconnection in the grey level case. Finally, it is proven that the implementation of this image processing machine is economically feasible.

Efficient shape transformations on a massively parallel processor

One of the most important features in image analysis is shape. Problems regarding shape are widely encountered in image processing applications, such as machine vision recognition, visually guided robots, analysis of biomedical images, etc. Mathematical morphology is the branch of image processing that deals with shape analysis. The definition of all morphological transformations is based on two primitive operations, namely dilation and erosion. Since many applications require the solution of morphological problems in real time, the efficient implementation of these operations, in terms of computational time, is crucial. In this paper, two algorithms for the dilation and erosion on an advanced associative processor are presented and evaluated. It is shown that these algorithms can take full advantage of the capabilities of the advanced architecture. Specifically, the ability to access all memory words in parallel leads to synchronous rapid execution of any image translation dictated by the structuring elements employed for morphological processing. The interconnection network allows the efficient implementation of image translations at any number of pixels. Also, the ability to perform logic operations parallel on the bits in each processing element leads to optimal computational complexity. Finally, it is shown that there is a trade-off between circuit complexity and communication delay.

A Parallel Solution in Texture Analysis Employing a Massively Parallel Processor

Texture is a fundamental feature for image analysis, classification, and segmentation. Therefore, the reduction of the time needed for its description in a real application environment is an important objective. In this paper, a texture description algorithm running over a hypercube massively parallel processor, is presented and evaluated through its application in real texture analysis. It is also shown that its hardware requirements can be tolerated by modern VLSI technology.

Efficient primitive binary morphological algorithms on a massively parallel processor

One of the most important features in image analysis and understanding is shape. Mathematical morphology is the image pro- cessing branch that deals with shape analysis. The definition of all morphological transformations is based on two primitive operations, i.e., dilation and erosion. Since many applications require the solu- tion of morphological problems in real time, researching time effi- cient algorithms for these two operations is crucial. In this paper, efficient algorithms for the binary dilation and erosion are presented and evaluated for an advanced associative processor. Simulation results show that the proposed algorithms for this advanced archi- tecture reach a near optimal speedup compared to the serial algo- rithm. Additionally, it is proven that the implementation of this image processor is economically feasible.

Sliding-Window Compression on the Hypercube

Dictionary compression belongs to the class of lossless compression methods and is mainly used for compressing text files [1, 2, 3]. In this paper, we present a parallel algorithm for one of these coding methods, namely the LZ77 coding algorithm also known as a sliding-window coding algorithm. Although there exist PRAM algorithms [4, 5] for various dictionary compression methods, their rather irregular structure has discouraged their implementation on practical interconnection networks such as the mesh and hypercube. However in the case of LZ77 coding, we show how to exploit the specific properties of the algorithm in order to achieve an efficient implementation on the hypercube.

A HYPERCUBE ALGORITHM FOR SLIDING WINDOW COMPRESSION

Dictionary compression belongs to the class of lossless compression methods and is mainly used for compressing text files. The most known examples of this technique are the algorithms of the LZ coding family whose common feature is the use of an adaptive dictionary which is dynamically adjusting during the algorithm execution. In this paper, we present a parallel algorithm for one of these coding algorithms, namely the LZ77 coding algorithm also known as a sliding-window coding algorithm. We also present a parallel algorithm for the corresponding LZ77 decoding algorithm. Although there exist PRAM algorithms for various dictionary compression methods, their rather irregular structure has discouraged their implementation on practical interconnection networks such as the mesh and hypercube. However in the case of LZ77 coding/decoding, we show how to exploit the specific properties of the algorithm in order to achieve an efficient implementation on the hypercube. Specifically, we show how to encode a N-character string on a N-node hypercube in only O(log2N) time. In contrast, a naive simulation of a PRAM algorithm of the LZ77 coding on the hypercube would have O(log3N) complexity. In addition, we further enhance the performance of our parallel algorithms by using some known heuristics from the field of text compression.

Hierarchical Block Matching Motion Estimation on a Hypercube Multiprocessor

Block matching motion estimation algorithms are widely used in video coding schemes. In this paper, we design an efficient hierarchical block matching motion estimation (HBMME) algorithm on a hypercube multiprocessor. Unlike systolic array designs, this solution is not tied down to specific values of algorithm parameters and thus offers increased flexibility. Moreover, the hypercube network can efficiently handle the non regular data flow of the HBMME algorithm. We also assume that our multiprocessor is fine grained in contrast to most programmable architectures used in video coding where processors usually have a large local memory. Apart from its practicality, the constraint of limited local memory makes the algorithm design more challenging and thus more theoretically interesting.