Andreas V. Bechtolsheim

Using dynamic buffer limiting to protect against belligerent flows in high-speed networks

Conventional QoS mechanisms have focused primarily on providing better than normal service for some flows over others. With networks moving to much higher speeds and reasonable provisioning, best efforts access to network resources is adequate for common applications except when a belligerent flow attempts to consume an excessive amount of bandwidth. Any mechanism that attempts to contain such a flow must be able to operate at wirespeed in hardware. In this environment, conventional QoS mechanisms are not sufficient, either because they do not have mechanisms to contain these belligerent flows or because they are not practical to implement in hardware. In this paper we describe dynamic buffer limiting (DBL), a buffer and queue management mechanism designed to recognize and handle belligerent flows at very high speed and suitable for hardware implementation.

FX1000: a high performance single chip Gigabit Ethernet NIC

We present the design of the FX1000, a high performance single chip Gigabit Ethernet NIC. With a 64 bit, 66 MHz PCI bus interface the chip can maintain a throughput of 2 Gbps between memory and the network. The 64-bit address also allows the FX1000 to address very large system memory. In addition, it transmits and receives packets with minimal assistance from the CPU. Furthermore, the FX1000 performs TCP checksum calculation and IEEE 802.1q virtual LAN processing in hardware.