Andreas Wiesbauer

A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion

An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications.

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A fully integrated WiMedia/MBOA-compliant RF transceiver for UWB data communication in the 3 to 5GHz band is presented. It is designed in a 0.13mum standard CMOS process with 1.5V single supply voltage. The NF is between 3.6 and 4.1dB over all 3 bands. On the TX side, the P1dB is 5dBm supporting an EVM of -28dB and up to -4dBm output power. A single-PLL LO generation is included

Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters

A power amplifier (PA) using the distributed amplifier technique for the ultra wideband (UWB) standard is presented. The amplifier is fabricated in a standard 0.13 /spl mu/m CMOS technology and comes with on-chip biasing circuitry and a non-distributed input stage. Measurement results are given for a chip-on-board module to take any influence of product assembly into account. It achieves a transmission coefficient S/sub 21/ = 17 dB, a corner frequency of f/sub c/ = 8 GHz and a 1 dB compression point of A/sub 1dB/ = 3.5 dBm. The output impedance is matched to 50 /spl Omega/ so that external matching circuitry can be omitted. With these features, it is customized to be integrated with other building blocks to a fully integrated CMOS UWB transmitter product.

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction

This work presents a system level model of the clock jitter influence in certain types of continuous time sigma delta modulators. The model helps the design of such modulators by speeding up the simulations, predicting analytically the SNR degradation and providing a practical way to minimize the jitter sensitivity of the modulator. Simulations and theoretical developments are contrasted with measurements in a real chip.

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter

An analog to digital conversion scheme based on an Asynchronous SigmaDelta Modulator is presented. It uses a Time-to-Digital converter to convert the continuous-time square wave signal produced by the Asynchronous SigmaDelta Modulator to a time-quantized digital signal. The original input signal is then recovered by applying a digital demodulation algorithm derived from general duty-cycle modulation theory. This technique shifts the complexity towards the digital domain and is therefore especially suited for ultra-low voltage technologies beyond 90 nm. Simulations show 13 bit accuracy for Bluetooth baseband 500 kHz with a first-order SigmaDelta modulator and a Time-to-Digital Converter with 10 ps resolution running at 12 MHz. Using a second-order feedback system to shape the quantization noise of the Time-to-Digital converter, the bandwidth can be increased to 12 MHz with 12 bit accuracy, suitable for video applications.

A power optimized 14-bit SC /spl Delta//spl Sigma/ modulator for ADSL CO applications

A switched-capacitor multi-bit /spl Delta//spl Sigma/ ADC including a reference-voltage buffer is implemented in 0.13 /spl mu/m CMOS. The single loop 3 b modulator features 14 b and 13 b dynamic range over 276 kHz and 1.1 MHz signal bandwidths, respectively. Clocked at 105 MHz, the ADC core consumes 8 mW from a 1.5 V supply.

A 0.1 mm

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm2.

^{2}

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.

, Wide Bandwidth Continuous-Time

A 300MHz all-digital differential VCO-based ADC occupies 0.02mm2 in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.

\Sigma\Delta

A time-interleaved architecture overcomes the dynamic performance limitations of standard DWA switching. Clocked at 350MHz, the DAC with active output buffer achieves a linearity of 76dB for a signal swing of 1.536V and an effective resolution of 11.9b in a bandwidth of 29.16MHz. It is fabricated in a standard 0.13 /spl mu/m CMOS process and consumes 62mW from a 1.5V supply.