Andrew Bardsley

SPA - a synthesisable Amulet core for smartcard applications

SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system.

Compiling the language Balsa to delay insensitive hardware

A silicon compiler, Balsa-c, has been developed for the automatic synthesis of asynchronous, delay-insensitive circuits from the language Balsa. Balsa is derived from CSP with similar language constructs and a single-bit granularity type system.

Synthesising an asynchronous DMA controller with balsa

A DMA controller has been designed and implemented as part of the AMULET3i asynchronous microprocessor macrocell using a mixture of synchronous and asynchronous circuit techniques. The synthesis language Balsa has been used to implement the major part of the controller, the asynchronous control. The use of Balsa has allowed the controller to be rapidly re-engineered in response to a changing specification.

SPA - A Secure Amulet Core for Smartcard Applications

Abstract SPA is a synthesised, self-timed, ARM-compatible processor core designed for use in security-sensitive applications. It was incorporated in an experimental smartcard chip which is being used to evaluate the applicability of self-timed logic in secure devices. The system-on-chip was synthesised using the Balsa synthesis system with only a small amount of hand design employed to boost the throughput of the on-chip interconnect. The use of synthesis was mandated by a need for rapid implementation and Balsa proved to be very effective: SPA required only 25% of the design effort of earlier non-synthesised Amulets. Balsa was modified to generate circuits with enhanced security against non-invasive attacks. Initial analyses indicate that the secure SPA achieved up to 80% improvement in resistance against non-invasive attacks albeit at the cost of reduced performance and increased area and power consumption.

Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus

For todays SoC designer, on-die variation, clock distribution, timing closure, and power concerns confront the desire to get products to market quicker. Each new process generation makes the challenge greater as process skews, complexity, and frequency become more onerous. This is particularly true for signals that have to travel across larger portions of a chip such as clocks and buses. In this paper, we examine the use of GALS (Globally Asynchronous, Locally Synchronous) [Chapiro, 1985] techniques to address on-chip communication between different synchronous modules on a bus. We explore issues related to validation, module interfaces and tool flows, while looking at advantages in power savings, timing closure and Time-to-Market/Time-to-Money (TTM). Our exploration vehicle is the IntelregPXA27x Peripheral Bus (PB) - a common interface for connecting peripherals on PXA27x and related processor families in Intels cellular and handheld application and communication domain.

Synthesising heterogeneously encoded systems

Self-timed datapaths require their data to be encoded in a delay-insensitive manner. The dual-rail encoding is commonly used, but more complex codes offer the possibility of better energy efficiency or fewer wires-per-bit. However, these advantages are often negated by datapath manipulations within large systems that require code-groups to be split and reformed. These overheads may be reduced by heterogeneously encoding circuits based on the datapath requirements within the circuits. In this paper, such an approach is evaluated within the Balsa asynchronous synthesis system. Techniques for synthesising arbitrary m-of-n encodings for datapath components are presented. These implementations allow each channel within a handshake circuit to be assigned an individual encoding. An automated encoding mechanism is described which analyses the datapath requirements of Balsa circuits and assigns codes to channels based on the interaction between sections of datapaths. The performance of the heterogeneous approach is evaluated on two microprocessor implementations

Performance-driven syntax-directed synthesis of asynchronous processors

The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthesis paradigm that compiles transparently a system specification written in a high-level language into a network of pre-designed handshaking modules. The transparency is provided by a one-to-one mapping from language constructs to the module networks that implement them. This gives the designer flexibility, at the language level, to optimise the resulting circuit in terms of performance, area or power. This paper introduces new techniques that exploit this flexibility to improve the performance of synthesised asynchronous systems. The results of a series of transistor level simulations show that these techniques, combined with optimised handshake module implementations, can produce close to a ten-fold improvement in the performance of a 32-bit, ARM-compatible, asynchronous processor used in an experimental smartcard SoC, without introducing any changes to the original processor architecture.

Description-Level Optimisation of Synthesisable Asynchronous Circuits

The syntax-directed synthesis paradigm has shown to be a powerful synthesis approach. However, its control-driven nature results in significant performance overhead. Some methods to reduce this overhead include peephole optimisations, control resynthesis and component optimisations. This work explores new methods of improving the performance of syntax-directed synthesised asynchronous circuits, using the Balsa synthesis system as the research framework. This includes investigating description styles and the usage of language constructs that exploit the directness of the synthesis method to obtain more concurrent and faster circuits. The techniques and optimisations presented here has been tested in a set of non-trivial examples including a 32-bit processor, a Viterbi decoder, and a channel-sliced wormhole router.