Andrew J. Norton

Diffuse large B-cell lymphoma outcome prediction by gene- expression profiling and supervised machine learning

Diffuse large B-cell lymphoma (DLBCL), the most common lymphoid malignancy in adults, is curable in less than 50% of patients. Prognostic models based on pre-treatment characteristics, such as the International Prognostic Index (IPI), are currently used to predict outcome in DLBCL. However, clinical outcome models identify neither the molecular basis of clinical heterogeneity, nor specific therapeutic targets. We analyzed the expression of 6,817 genes in diagnostic tumor specimens from DLBCL patients who received cyclophosphamide, adriamycin, vincristine and prednisone (CHOP)-based chemotherapy, and applied a supervised learning prediction method to identify cured versus fatal or refractory disease. The algorithm classified two categories of patients with very different five-year overall survival rates (70% versus 12%). The model also effectively delineated patients within specific IPI risk categories who were likely to be cured or to die of their disease. Genes implicated in DLBCL outcome included some that regulate responses to B-cell–receptor signaling, critical serine/threonine phosphorylation pathways and apoptosis. Our data indicate that supervised learning classification techniques can predict outcome in DLBCL and identify rational targets for intervention.

FPGA-Driven Table System to Accelerate Network Flows

Commercial products using hardware and firmware for high-speed network flow tracking are commonplace but typically restrict users to a few predefined options. Conversely, ensemble architectures with multiple network processing units (NPUs) and specialized accelerators are flexible enough for many tasks but relatively slow at routine flow management tasks. The paper presents a system that combines a field programmable gate array (FPGA)-driven table system with an ensemble network architecture. The system is especially effective when the FPGA system tracks flows and sends only selected packets to NPUs for further processing. The principal design goal is to achieve FPGA-level speed when processing tables for flows, actions, packet modification, key search and hash extraction and yet to allow users to initialize and dynamically modify the tables in terms of flexible, high-level packetC language types and structures.