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Dive into the research topics where Andrew Mawer is active.

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Featured researches published by Andrew Mawer.


Microelectronics Reliability | 2000

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

Robert Darveaux; Jim Heckman; Ahmer Syed; Andrew Mawer

Abstract The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used. Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages. Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40⇔125°C, 15 min ramps, 15 min dwells and 0⇔100°C, 10 min ramps, 5 min dwells.


electronic components and technology conference | 1999

Board-level characterization of 1.0 and 1.27 mm pitch PBGA for automotive under-hood applications

Andrew Mawer; Nick Vo; Zane Johnson; W. Lindsay

Ball grid array (BGA) has become the mainstream package of choice for devices with pin counts greater than 160. As such, the current generation of automotive engine and electronic transmission controllers for under-hood and on-engine mounting with pin counts in the 200 to 350 pin count range are being introduced by Motorola in BGA packaging. There is also a driving force to reduce the form factor of automotive electronics, both due to space constraints and to achieve lower material costs. All this is occurring while there is a shift to put more electronics under-hood and specifically on-engine, where temperatures can be greater than typical firewall mounting. One special concern with the BGA, therefore, is its ability to withstand the repeated cycling associated with these applications up to temperatures that can approach 150/spl deg/C. This paper will outline testing and simulation using finite element analysis (FEA) that was performed to assess the board-level (i.e., package to board interconnect) reliability of both 1.0 and 1.27 mm pitch PBGAs for the severe automotive environment. Variables such as package body size, die size, ball size, package substrate thickness, solder ball pitch and the presence/absence of thermal balls will be addressed. Solder joint fatigue failure data from the commonly used -40 to 125/spl deg/C automotive thermal cycling condition as well a more severe potentially required condition of -50 to 150/spl deg/C will be presented to show the suitability of PBGA for the intended application from a solder joint reliability perspective.


IEEE Transactions on Components and Packaging Technologies | 2003

The effect of modifications to the nickel/gold surface finish on assembly quality and attachment reliability of a plastic ball grid array (peer review version)

Richard J. Coyle; Diane E. Hodges Popps; Andrew Mawer; Donald P. Cullen; George M. Wenger; Patrick P. Solan

Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of standard and experimentally modified ENIG surface finishes. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.


electronic components and technology conference | 1999

Impact of solder pad size on solder joint reliability in flip chip PBGA packages

Lei L. Mercado; Vijay Sarihan; Yifan Guo; Andrew Mawer

A variety of package parameters impact package reliability. One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related. It was shown in this study that the solder pad size plays a big role in solder joint reliability. The difference in solder pad size due to different vendors and processes can affect the reliability considerably. In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness. Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored. In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages. The simulation results were experimentally validated with moire interferometry. Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate. However, the size of BGA solder pad was found to be crucial to BGA life. In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred.


Microelectronics Reliability | 2000

Simulation of fatigue distributions for ball grid arrays by the Monte Carlo method

John W. Evans; Jillian Y. Evans; Reza Ghaffarian; Andrew Mawer; Kyoung-Taeg Lee; Chang-Ho Shin

Abstract Any approach to qualification of advanced technologies during product development must include an assessment of variation expected in product life over the life cycle. However, testing product design options in development, to approach an optimal design is costly and time consuming. Hence, simulation of product life distributions for virtual qualification can be a valuable tool to evaluate and qualify design options. This paper presents a physics of failure-based approach to virtual qualification of advanced area array assemblies against solder fatigue failure. The approach applies Monte Carlo simulation to evaluate solder joint fatigue life distributions, given material property variations and manufacturing capabilities. Preliminary results using the simple Engelmaier model as the basis of simulations are presented. Simulation results are compared to data accumulated from two test environments and two ball grid array product types. The results reveal some of the limitations of the Engelmaier model as a basis for simulation. They also show the potential of this approach to virtual qualification for design and manufacturing capability assessment in development.


Materials Chemistry and Physics | 1995

Plastic ball grid array (PBGA) overview

Jay J. Liu; Howard M. Berg; Yenting Wen; Shailesh Mulgaonker; Reed Bowlby; Andrew Mawer

As integrated circuit functionality and clock speed continue to rise, innovative packaging approaches are in great demand. Recently, the plastic ball grid array (PBGA) technology has been gaining industry-wide interest and commitment as the potentially lowest-cost package for high-I/O devices and even for some lower-pincount applications. Drivers include the density advantages of an area array, quickly achieving six-sigma assembly yields with existing assembly equipment, the potential for excellent electrical and thermal performance, along with the traditional low cost of plastic packages. Because some perceived weaknesses are being eradicated, worldwide evaluation of the PBGA has accelerated. Although various aspects of this technology are discussed frequently, an overall assessment is still under development. In this paper, a systematic and comprehensive evaluation of PBGA technology will be described to identify (1) its technical advantages and limitations, (2) unique application areas where PBGA is the package of choice, and (3) current major hurdles for acceptance of PBGA and possible approaches to overcome these problems. The PBGA will be compared with PQFP, CQFP and CBGA in terms of package characteristics and their impact on system assembly. The characteristics include package attributes (i.e., package size, I/O counts and lead pitch), performance (i.e., electrical, thermal) and reliability (moisture). At the system level, solder joint fatigue, board routing, solder assembly yield, solder reparability and board delay are key metrics. The cost implication of various package families will be discussed. By analogy with SMT, the infrastructure for PBGA will take time to develop. The key elements and the current status of this infrastructure will be discussed.


electronic components and technology conference | 2001

The effect of variations in nickel/gold surface finish on the assembly quality and attachment reliability of a plastic ball grid array

Richard J. Coyle; George M. Wenger; Diane E. Hodges; Andrew Mawer; Donald P. Cullen; Patrick P. Solan

Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of four variations of the ENIG surface finish. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.


2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1 | 2003

Crack Area Analysis of SnPb and SnAg Solder Joints in Plastic Ball Grid Array Packages From Dye Penetration Studies

Changyoung Park; Jose Marcio Dias Filho; Donghyun Kim; Andrew Mawer; Glenn Y. Masada; Tess J. Moon

Crack growth in solder joints caused by thermal cycling is a critical issue for reliability in electronic packages. This study presents experimental data on crack growth in SnPb and SnAg solder joints of 357-joint PBGA packages attached to PWBs and subjected to 30-minute, 0°C to 100°C temperature cycles. The board assemblies were exposed to three process conditions upon exiting the solder reflow furnace—air cooled to room temperature, quenched at 0°C, and aged at 150°C (SnPb) or 160°C (SnAg) for 1008 hours—prior to the accelerated thermal cycle testing. At scheduled intervals, the packages were dye-penetrated, removed from the board, and the joint crack areas in several regions measured. The experimental data and statistical analysis of 9000 joints show that SnAg solder joints have half the crack areas of their SnPb counterparts for all regions, cycles and aging conditions. For both solders, the joints located under the die edge have the largest cracks of any region, and the three adjacent joints at each of the four corners under the die edge are the joints most likely to have the largest crack areas. Comparing aging conditions, the differences in the means of % crack area for SnPb packages were not statistically different, but for SnAg packages, the aged joints had 50% smaller crack areas than non-aged joints (air and quench).Copyright


2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1 | 2003

Life Prediction of SnPb and SnAg Solder Joints in PBGA Packages Using a Severity Metric

Donghyun Kim; Andrew Mawer; Tess J. Moon; Glenn Y. Masada

A severity metric is developed to predict the life of SnPb and SnAg solder joints in PBGA packages by quantitatively estimating the changes in damage arising from different board configurations and accelerated thermal cycle tests (ATC). Damage measures include time-dependent creep, time-independent plastic deformation, and an effective stress that is computed from the ATC parameters of temperatures, dwell-time, and ramp rates and from package geometries on the printed wiring board. Life prediction using this severity metric has been applied to 24 sets of test data on SnPb and SnAg solder joints in 357-PBGA packages and include three post-processing conditions (aged at 150/160°C, quenched at 0°C, and air-cooled), three ATC test conditions (0–100°C, −40–125°C, and −55–125°C), and four package-on-board geometric configurations. Statistical analysis is provided to compare the life predictions based upon the severity metric and from ATC testing—predicted joint life is well within one standard deviation of the experimental mean value of life for most of the 24 cases. The severity metric can be used to quantify the effects of design and manufacturing choices on joint life.Copyright


Archive | 2001

Board-Level Area Array Interconnect Reliability

Thomas H. Koschmieder; Andrew Mawer; Giulio Di Giacomo; Jasvir Singh Jaspal

The objective of reliability engineering is to provide the capability of predicting the percentage of field cumulative failures at the end of life with a certain degree of confidence, based on the statistical distribution of the data and on the acceleration factor determined by testing. There are, therefore, bounds on confidence limits which accompany the median time-to-failure, the standard deviation of the data and projected fail fraction. As with the die-level, board level area-array solder joint, tests are used to verify semi-empirical models based on failure data.

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Donghyun Kim

Kennesaw State University

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Glenn Y. Masada

University of Texas at Austin

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Tess J. Moon

University of Texas at Austin

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Changyoung Park

University of Texas at Austin

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Jillian Y. Evans

Goddard Space Flight Center

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