Andrew Metz

TRENCH AND HOLE PATTERNING WITH EUV RESISTS USING DUAL FREQUENCY CAPACITIVELY COUPLED PLASMA (CCP)

Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process. In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Resist process applications to improve EUV patterning

Roughness control is a key technical issue in extreme ultraviolet (EUV) lithography. It applies to both line and space (L/S) and contact hole (C/H) structures. Recently, SEMATECH and Tokyo Electron Limited (TEL) developed several track-based techniques, including developer optimization, FIRM™ (Finishing up by Improved Rinse Material), and smoothing to reduce structural roughness. The combination of these techniques improved line width roughness (LWR) about 25% from the 2011 baseline of 32 nm L/S. C/H structures were also tested with the combination process. This paper describes our latest L/S and C/H roughness performance post-lithography and postetch. A feasibility study of negative tone develop (NTD) resists for EUV is also included.

Utilization of spin-on and reactive ion etch critical dimension shrink with double patterning for 32 nm and beyond contact level interconnects

Spin-on chemical shrink, reactive ion etch [RIE] shrink and litho-etch-litho-etch [LELE] double patterning have been utilized to produce dense 90 nm pitch, 26 nm bottom CD contacts starting from 65 nm CD, 126 nm diagonal pitch as printed features. Demonstrated lithographic process window, post etch pattern fidelity, CD, and CD uniformity are all suitable to production. In addition, electrical test results shows a comparable defect a ratio vs. a no chemical shrink baseline.

Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

DSA via hole shrink for advanced node applications

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.

Evaluation of novel processing approaches to improve extreme ultraviolet (EUV) photoresist pattern quality

Recently there has been a great deal of effort focused on increasing EUV scanner source power; which is correlated to increased wafer throughput of production systems. Another way of increasing throughput would be to increase the photospeed of the photoresist used. However increasing the photospeed without improving the overall lithographic performance, such as local critical dimension uniformity (L-CDU) and process window, does not deliver the overall improvements required for a high volume manufacturing (HVM). This paper continues a discussion started in prior publications [Ref 3,4,6], which focused on using readily available process tooling (currently in use for 193 nm double patterning applications) and the existing EUV photoresists to increase photospeed (lower dose requirement) for line and space applications. Techniques to improve L-CDU for contact hole applications will also be described.

Towards production ready processing with a state-of-the-art EUV cluster

EUV lithography is one of the main candidates for enabling the next generation of devices, primarily by enabling a lithography process that reduces complexity, and eventually, cost. IBM has installed the latest tool sets at the IBM EUV Center of Excellence in Albany to accelerate EUV lithography development for production use. Though the EUV cluster is capable of enabling the pitch requirements for the 7nm node, the dimensions in question represent a new regime in defectivity. Additionally, new classes of patterning materials are being explored, for which there is very little known up-front regarding known defect mechanisms. We will discuss the baseline cluster performance and the improvement strategy in terms of defectivity and pattern collapse in this paper by utilizing coater/developer techniques based on the new platform.

Co-optimization of lithographic and patterning processes for improved EPE performance

Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone. To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes. Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

EPE improvement thru self-alignment via multi-color material integration

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line. In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.