Andrey Lutich

Design space sampling using hierarchical clustering of patterns on a full chip

This research considers problem of sampling design space of a given physical design layout. More specifically, it deals with extraction of a set of characteristic design patterns evenly distributed within design space occupied by the layout. The methodology reported here is capable of condensing large design layouts comprised of billions of patterns to few tens of representative cases fulfilling needs of process development and process monitoring in a semiconductor manufacturing facility as well as for OPC and process compensation setup. Patterns extracted by this method include both patterns having high representation in the incoming design and anomalous configurations. In the case study we have sampled design space of a 22FDX test chip with 40 mm2 area on a contact layer. Incoming design layout comprised of 763.6 million patterns has been condensed to 61 patterns that contained all anticipated design configurations as well as a couple of unexpected findings. Extractions of compact pattern representations and multi-step hierarchical clustering method enabling full chip execution (106-1010 patterns) are discussed here in detail.

Design space analysis of novel interconnect constructs for 22nm FDX technology

In this paper, we describe an integrated design space analysis approach consisting of full factorial layout generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and cell boundary situations, which are critical for a place and routed block. These interconnects developed using the integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.

Improving contact layer patterning using SEM contour based etch model

The patterning of the contact layer is modulated by strong etch effects that are highly dependent on the geometry of the contacts. Such litho-etch biases need to be corrected to ensure a good pattern fidelity. But aggressive designs contain complex shapes that can hardly be compensated with etch bias table and are difficult to characterize with standard CD metrology. In this work we propose to implement a model based etch compensation method able to deal with any contact configuration. With the help of SEM contours, it was possible to get reliable 2D measurements particularly helpful to calibrate the etch model. The selections of calibration structures was optimized in combination with model form to achieve an overall errRMS of 3nm allowing the implementation of the model in production.

Optimal structure sampling for etch model calibration

Successful patterning requires good control of the photolithography and etch processes. While compact litho models, mainly based on rigorous physics, can predict very well the contours printed in photoresist, pure empirical etch models are less accurate and more unstable. Compact etch models are based on geometrical kernels to compute the litho-etch biases that measure the distance between litho and etch contours. The definition of the kernels as well as the choice of calibration patterns is critical to get a robust etch model. This work proposes to define a set of independent and anisotropic etch kernels designed to capture the finest details of the resist contours and represent precisely any etch bias. By evaluating the etch kernels on various structures it is possible to map their etch signatures in a multi-dimensional space and analyze them to find an optimal sampling of structures to train an etch model. The method was specifically applied to a contact layer containing many different geometries and was used to successfully select appropriate calibration structures. The proposed kernels evaluated on these structures were combined to train an etch model significantly better than the standard one.

Contour-based etch modeling enablement: from pattern selection to final verification

Traditional CD-SEM metrology reaches its limits when measuring complex configurations (e.g. advanced node contact configurations). SEM extracted contours embody valuable information which is essential for building a robust etch prediction model [1, 2]. CDSEM recipe complexity, processing time and measurement robustness can be improved using contour based metrology. However, challenges for measurement pattern selection as well as final model verification arise. In this work, we present the full flow of implementing etch prediction models calibrated and verified with SEM contours into a manufacturing environment.

Pattern sampling for etch model calibration

Successful patterning requires good control of the photolithography and etch processes. While compact litho models, mainly based on rigorous physics, can predict very well the contours printed in photoresist, pure empirical etch models are less accurate and more unstable. Compact etch models are based on geometrical kernels to compute the litho-etch biases that measure the distance between litho and etch contours. The definition of the kernels as well as the choice of calibration patterns is critical to get a robust etch model. This work proposes to define a set of independent and anisotropic etch kernels –“internal, external, curvature, Gaussian, z_profile” – designed to capture the finest details of the resist contours and represent precisely any etch bias. By evaluating the etch kernels on various structures it is possible to map their etch signatures in a multi-dimensional space and analyze them to find an optimal sampling of structures to train an etch model. The method was specifically applied to a contact layer containing many different geometries and was used to successfully select appropriate calibration structures. The proposed kernels evaluated on these structures were combined to train an etch model significantly better than the standard one. We also illustrate the usage of the specific kernel “z_profile” which adds a third dimension to the description of the resist profile.

Hybrid pattern matching based SRAF placement

A hybrid multi-step method for Sub-Resolution Assist Feature (SRAF) placement is presented. The process window, characterized by process variation bands (PV-bands), is subjected to optimization. By applying a state-of-the-art advanced pattern matching based approach, the SRAF placement is optimized to maximize the process window. Due to the complexity of building a complete Rule-Based SRAF (RBSRAF) solution and the performance limitation of the Model-Based SRAF solution (MBSRAF), the hybrid pattern based SRAF reduces the complexity and improves performance. In this paper, the hybrid pattern-based SRAF algorithm and its implementation, as well as testing results, are discussed with respect to process window and performance.

SRAF insertion for VIA-like layers using laSRAF method

A novel Sub-Resolution Assist Feature (SRAF) insertion approach is discussed. The method of linearly added SRAFs (laSRAF) is based on the superposition, linear addition in the simplest case, of pre-calculated SRAF usefulness templates. The usefulness templates describe net effect of an elementary SRAF insertion in the proximity of an isolated arbitrary target shape. The method includes two major steps: (i) SRAF usefulness map generation for arbitrary layout comprised of OPC target shapes and (ii) derivation of Mask Rule Check (MRC) compliant SRAF shapes from those usefulness maps. The performance of the laSRAF method measured by the run-time and process window enhancement effect is compared to production quality model-based SRAF insertion implementations and one rule-based realization. The comparison reveals up to 8 times faster SRAF insertion at the same or better SRAF quality with the laSRAF method compared to model-based solutions. LaSRAF has been found to be significantly superior in terms of SRAF quality at the penalty of 2-4x longer run-time compared to rule-based SRAF.

Alternative to ILT method for high-quality full-chip SRAF insertion

A novel approach to Sub-Resolution Assist Feature (SRAF) generation suitable for full-chip production scale applications is discussed in this work. The method enables generation of free-form SRAF insertion guidelines similar to those obtained by solving the inverse lithography problem. The guidelines encompass layout areas where total net effect of an elementary SRAF placement is positive taking into account all neighboring target features. The essence of the method is the assumption that the total impact of placing an elementary SRAF close to several neighboring features can be calculated as a sum of impacts to individual target features, or a simple mathematical function could be used to perform this calculation. Reduction of the SRAF insertion problem to the linear addition of “usefulness” metric on a grid enables the method to be exceptionally computationally efficient. Tests on an aggressive 28nm 100x100 um design contact array clips have confirmed 3+ orders of magnitude faster free-form SRAF generation as compared to commercially available ILT engines.

A stochastic approach to SRAF printing prediction

In this paper we discuss a statistic approach to SRAF printing detection. This method considers and is generically based on the opportunistic essence of the resist image formation due to various stochastic uncertainties in the state-of-the-art advanced node lithographic process. The method is based on the direct measurement of the probability of SRAF printing at considered-to-be-nominal conditions and extrapolation of the results based on the process conditions/assumptions to the probability ranges where direct probability measurements are practically impossible. The method described here provides a controllable and quantitative framework for setting up SRAF printing detection and facilitates the significant reduction of the efforts and costs needed to setup SRAF printing checks. The argumentation and the way of looking at the verification setup in the environments with considerable variability can be directly reused to design and calibrate other checks in OPC verification flows.