Andy Peczalski

Military/civilian mixed-mode Global Positioning System (GPS) receiver (MMGR)

This paper describes plans and progress made on the MMGR program funded jointly by Air Force Research Laboratory (AFRL), GPS Joint Program Office (JPO) and industry that started in April 2003. The Honeywell/Rockwell Collins MMGR program starts with a minimum configuration of the GPS receiver (e.g. low end commercial GPS) and develop a new RF front-end design using mixed mode CMOS technology with lowest cost components and processes over the first year of the program. The front-end Application Specific Integrated Circuit (ASIC) design have a modular and flexible architecture based on reuseable macro-cells. This initial RF front-end design is evolved and targeted to meet specific commercial, military and space application requirements during the subsequent development iterations over the last two years of the program and beyond. Rockwell Collins demonstrates feasibility of using a digital device to create an M-code capable, high anti-jam GPS system. This shows a path to an adaptable MMGR that enables flexibility and easy upgradeability for both military and commercial GPS receivers and adheres to GPS Modernization/GPS III receiver specifications. The emphasis of the Rockwell Collins task is to improve anti-jam (AJ) and anti-interference capability of the GPS receivers through miniaturization of the anti-jamming (AJ) electronics and improvements in ultra-tight coupling (UTC) of a GPS receiver and an Inertial Measurement Unit (IMU).

RF/analog/digital SOI technology for GPS receivers and other systems on a chip

Increasing numbers of military and aerospace systems require miniaturization and low power which can only be achieved by employing mixed mode combinations of RF, analog and digital circuits on the same chip. GPS receivers are an excellent example of the subsystem required to fit in small munitions or the soldier watch. At the same time, the requirements for jamming and spoofing resistance and encryption decoding increase the gate count to 20-30 Mgates. Similar in complexity the analog section may require 16-bit analog to digital converter for digital beam forming. Demanding RF front-end performance section includes the low noise amplifiers with noise figure below 2 dB and with associated gain of 30-40 dB. Such extreme mixed mode requirements can be only met with specialized technology like Silicon-on-Insulator (SOI) on high resistivity substrate. Such substrate provides excellent isolation and 10 dB lower noise than in bulk CMOS.