Angel Abusleme

Noise in Charge Amplifiers—A

Charge amplifiers represent the standard solution to amplify signals from capacitive detectors in high energy physics experiments. In a typical front-end, the noise due to the charge amplifier, and particularly from its input transistor, limits the achievable resolution. The classic approach to attenuate noise effects in MOSFET charge amplifiers is to use the maximum power available, to use a minimum-length input device, and to establish the input transistor width in order to achieve the optimal capacitive matching at the input node. These conclusions, reached by analysis based on simple noise models, lead to sub-optimal results. In this work, a new approach on noise analysis for charge amplifiers based on an extension of the gm/ID methodology is presented. This method combines circuit equations and results from SPICE simulations, both valid for all operation regions and including all noise sources. The method, which allows to find the optimal operation point of the charge amplifier input device for maximum resolution, shows that the minimum device length is not necessarily the optimal, that flicker noise is responsible for the non-monotonic noise versus current function, and provides a deeper insight on the noise limits mechanism from an alternative and more design-oriented point of view.

g_{m}/I_{D}

One of the major problems for the massive applicability of electric vehicles (EVs) is the scarce capacity of conventional electrical energy storage systems. Although this constraint has been overcome in many cases using advanced technologies such as fuel cells and high-capacity batteries, it is still difficult to develop an economically viable and socially acceptable EV for massive use. In this context, solar energy is not a practical solution for satisfying this lack of energy. However, if a particular situation is considered, in which a small-sized, high-efficiency EV operates at low duty cycles in a sunny, predictable environment, solar power can become a solution for reducing transport costs. This paper deals with the reach of this approach.

Approach

FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltage-controlled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memristive circuits and prove its synaptic properties in a small associative memory via a perceptron ANN.

Improved performance of a battery powered electric car, using photovoltaic cells

Digital correlated double sampling (DCDS), a readout technique for charge-coupled devices (CCD), is gaining popularity in astronomical applications. By using an oversampling ADC and a digital filter, a DCDS system can achieve a better performance than traditional analogue readout techniques at the expense of a more complex system analysis. Several attempts to analyse and optimize a DCDS system have been reported, but most of the work presented in the literature has been experimental. Some approximate analytical tools have been presented for independent parameters of the system, but the overall performance and trade-offs have not been yet modelled. Furthermore, there is disagreement among experimental results that cannot be explained by the analytical tools available. In this work, a theoretical analysis of a generic DCDS readout system is presented, including key aspects such as the signal conditioning stage, the ADC resolution, the sampling frequency and the digital filter implementation. By using a time-domain noise model, the effect of the digital filter is properly modelled as a discrete-time process, thus avoiding the imprecision of continuous-time approximations that have been used so far. As a result, an accurate, closed-form expression for the signal-to-noise ratio at the output of the readout system is reached. This expression can be easily optimized in order to meet a set of specifications for a given CCD, thus providing a systematic design methodology for an optimal readout system. Simulated results are presented to validate the theory, obtained with both time- and frequency-domain noise generation models for completeness.

A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.

Optimal CCD readout by digital correlated double sampling

Discrete-time filters represent a promising solution for pulse-processing in high-energy physics experiments due to their flexibility, reliability, and their capability to synthesize weighting functions with virtually any shape. One of the major concerns when designing one of these filters is to calculate the filter parameters that maximize the signal-to-noise ratio. The classic way to address this problem is to perform the noise analysis using a continuous-time domain approach based on the weighting function concept. However, when addressing the problem from an inadequate time domain, the analysis is not insightful and the resulting expressions are complex and difficult to use for design purposes. In this work, a mathematical framework for a design-oriented analysis of discrete-time filters in the discrete-time domain is presented. This analysis is based on treating the sampled noise as a discrete-time signal, which can be manipulated to obtain a closed-form expression for the front-end noise, suitable for computer automatic evaluation and filter optimization procedures. An example of the optimum filter formulation and computation is presented, in addition to several conclusions about optimum digital filtering.

Crossbar-Based Memristive Logic-in-Memory Architecture

The BeamCal detector, one of the calorimeters in the forward region of the International Linear Collider detector, will serve three purposes: ensure hermeticity of the detector for small polar angles, reduce the backscattering from beamstrahlung electron-positron pairs into the detector center, and provide a low-latency signal for beam diagnostics. The BeamCal specifications in terms of noise suppression, signal charge, pulse rate, and occupancy pose unique challenges in the front end and readout electronics design. The Bean-BeamCal instrumentation IC is the integrated circuit under study to fulfill these requirements. To process the signal charge at the International Collider pulse rate, the Bean uses switched-capacitor filters and a slow reset-release technique. Each channel has a 10-bit successive approximation analog-to-digital converter. The Bean also features a fast feedback adder capable of providing a low latency output for beam diagnostic purposes. This work presents the design and characterization of a 3-channel prototype of the Bean built to validate concepts while the final device will comprise 32 channels.

Noise Analysis in Pulse-Processing Discrete-Time Filters

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

BeamCal Instrumentation IC: Design, implementation and test results

The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multi-level programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <1% tuning precision, on average 3x faster than another accurate tuning algorithm of the recent literature.

Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator

With the adoption of new technology nodes q for analog circuits, different digital techniques have been designed to enhance their performance. Among the existing techniques, a promising approach is to adapt the circuit operation dynamically considering the application characteristics. In the field of analog-to-digital converters (ADCs), typically this approach is carried out by taking advantage of application-dependent signal properties, hence their use is limited. In this work, a digital assistance technique for power reduction in ADCs is presented. By defining a reduced valid range for the next sample based upon the maximum possible change of the input signal between samples, the proposed algorithm reduces the mean energy consumption per conversion in a variety of ADC architectures, regardless of the application.