Angelo Magri

Integration of Melting Excimer Laser Annealing in Power MOS Technology

The integration of excimer laser annealing (ELA) into the power MOS device technology has been studied and evaluated. The integration issues include patterning effect, extreme nonequilibrium kinetics of dopant and defects, material modification due to the melting-regrowth phenomena (in the melting regime), and residual implant damage. We demonstrated that ELA can be applied as a reliable, effective, and advantageous process in the context of semiconductor device fabrication. In particular, power MOS field-effect transistors were successfully fabricated with superior electrical characteristics than those fabricated according to the standard process. Optimization of the process was achieved through extensive characterization analyses, while an intense research effort was dedicated to the development of a technology computer-aided design tool for the simulation of the laser annealing process in Si-based devices. The electrical characterization of the transistor fabricated by ELA is presented, showing a device yield of 90 % on wafer

Negative Bias Temperature Stress Reliability in Trench-Gated P-Channel Power MOSFETs

In this paper, we present the results of an experimental analysis of the degradation induced by negative-bias temperature stress (NBTS) in trench-gated p-channel power MOSFETs. Threshold voltage and carrier mobility are affected by hole trapping in bulk oxide and interface-state generation due to oxide electric field effects. A fast recovery phase occurs when gate bias is removed or reduced in order to measure the threshold voltage. Hence, various techniques for evaluating threshold voltage shift are adopted in order to highlight the differences in the dynamics of degradation. We investigate the influence of gate bias levels during the stress. Moreover, with the help of recovery studies, we try to distinguish the impact of interface-state generation and charge trapping on the NBTS degradation.

Understanding negative bias temperature stress in p-channel trench-gate power MOSFETs by low-frequency noise measurement

In this paper we analyze LF noise in trench-gate power MOSFETs to investigate the effect of negative bias temperature stress on the gate dielectric quality. We study how the amount of stress time influences both the threshold voltage and the trap density within gate oxide. After the stress, recovery conditions are applied to the device and its properties, in terms of threshold voltage, on-current and trap density, are analyzed. The present study allows to identify permanent and recoverable mechanisms associated to the applied stress.

Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

In this paper, we present a combined measurement/simulation method, implemented in order to estimate the spatial and energy oxide trap distribution induced by negative bias temperature instability (NBTI) stress in p-channel power U-MOSFETs. The methodology consists in analyzing the recovery phase at different bias conditions and correlating the results with TCAD numerical simulations. We found an oxide trap distribution positioned between 2.24 and 3.04 nm distant from oxide/channel interface with an energy level confined in the silicon bandgap.

NBTI in p-channel power U-MOSFETs: Understanding the degradation and the recovery mechanisms

In this paper, we present an analysis of the degradation mechanisms in p-channel power U-MOSFETs due to Negative Bias Temperature Instability (NBTI). In particular, we study the influence of NBTI on threshold voltage and trans-conductance, which are the main figures of merit affected by charges trapping in the bulk oxide and by an interface defects generation. At the end of the stress, a recovery phase is implemented in order to monitor permanent and recoverable degradation. Moreover, we investigate the influence of the overall channel area on the threshold voltage degradation and on device lifetime.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.