Anirban Sengupta

A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels

Abstract This paper presents an integrated design space exploration of scheduling and allocation problem in high level synthesis using the heuristic based multi structure genetic algorithm. A cost function based on a combination of power consumption and pipelined execution time as well as a scheme to select functional unit type in case of multiple versions is proposed that can guide the genetic algorithm to near-optimal/optimal solution. The cost function model takes the functional units, registers, multiplexers and demultiplexers into consideration. The encoding process of the parent chromosome incorporates a special seeding process that enables the genetic algorithm to search for an optimal solution. This type of seeding process was specifically incorporated because the optimal solution to a problem always lies between the maximum serial and parallel implementation. Therefore it is always capable of finding a near-optimal/optimal solution to the combined problem of scheduling and allocation based on the provided user specified constraints. Results of the comparison with another recent genetic algorithm based exploration technique indicated considerable reduction of execution clock cycle as well as power consumption for almost all the benchmarks.

Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration

This paper presents a novel multi structure genetic algorithm based design space exploration system which concurrently solves the problem of integrated scheduling, allocation and binding in High Level Synthesis based on the user specified power consumption and execution time constraints (not just latency constraint). The proposed novel cost function based on power consumption and execution time considers functional units, registers, multiplexers, demultiplexers and clock frequency oscillator during the exploration process. The presented approach incorporates a new seeding process for the two special parent chromosomes as well as employs a novel ‘load factor heuristic’ which guarantees that the final solution found will always be optimal/near-optimal in terms of the user specified execution time and power constraints. The results of the final solution reflect the number of adders/subtractors, multipliers, clock frequency, multiplexers, demultiplexers and registers. Further, the final result also indicates the latency, execution time, power consumption and the optimal/near-optimal resource combination found. The proposed approach when verified for number of standard DSP benchmarks yielded superior results compared to a recent GA based heuristic approach.

A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective

This paper introduces a novel approach to rapid Design Space Exploration (DSE) and presents a formalized High Level Synthesis (HLS) design flow with multi-parametric optimization objective using the same design space exploration approach. The proposed approach resolves issues related to DSE such as the precision of evaluation, time exhausted during evaluation and also automation of the exploration process. During DSE a conflicting situation always exists for the designer to concurrently maximize the accuracy of the exploration process and minimize the time spent during DSE analysis. This technique is capable of drastically reducing the number of architectural variants to be analyzed for accurate selection of the optimal design point in a short time. Unlike other proposed DSE approaches, the focus here is on determining the Priority Factor (PF) of the resources for final organization of the design space in increasing or decreasing order without requiring graphs or hierarchical tree arrangements to analyze the candidate variants. The proposed approach is capable of simultaneously optimizing many performance parameters viz. time of execution, power consumption, hardware area and cost. The DSE results for many benchmarks are presented along with a comparison with an existing DSE approach that uses the hierarchal structure method for architecture evaluation. Results indicated significant improvement in speedup compared to the existing approach.

A framework for fast design space exploration using fuzzy search for VLSI computing Architectures

In High level Synthesis design methodology, the evaluation and selection of the optimal architecture for the system is done through a process called Design Space Exploration (DSE). This paper presents a novel framework for fast DSE using fuzzy search technique for optimizing modular computing architecture for the current generation of multi objective VLSI designs. The proposed method is able to radically reduce the number of architectural variants to be analyzed during design space exploration while simultaneously maintaining the precision required during the exploration process. Significant improvement in speedup during DSE is obtained for different benchmarks, compared to a DSE method with binary search mechanism.

Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems

Abstract Design Space Exploration (DSE) with multi-parametric objective in High Level Synthesis (HLS) involves assessing the various design points in the architecture design space to find the optimum solution for the design according to the system requirements specified. Due to the time to market pressure, the cost of solving the problem of architecture selection by exhaustive analysis is strictly forbidden. The tradeoffs linked to the selection of the appropriate design point during architecture evaluation needs careful assessment for efficient design space exploration. Further DSE requires satisfying multiple conflicting multi objective conditions such as increase in accuracy of evaluation during DSE with simultaneous speedup in the exploration process. This paper presents a novel hybrid design space exploration approach which is a combination of the Priority Factor (PF) method and Fuzzy search technique that is rapid and accurate in architecture evaluation and selection. The proposed approach for DSE when applied on a number of benchmarks yielded superior results compared to the current existing DSE approach for architecture selection. The comparison results of the proposed hybrid approach with the current existing approach for different benchmarks are shown and the speedups obtained are also presented.

A novel framework of Optimizing modular computing architecture for multi objective VLSI designs

For the past few years modular design has become the de facto standard for the development of complex VLSI systems. Most of these modular VLSI system designs are generally multi objective in nature with the requisite to tradeoff between many contradictory parameters like speed, power consumed, cost and hardware area. They are heavily used in low end ASICs which demand low power consumption and cost with acceptable performance and in high end ASICs with high performance requirement. This paper presents a novel framework for the optimization of computing architecture based on hierarchy factor method. The determination of this hierarchy factor enables the designer to arrange the various resources of the system in the form of an architecture tree based on the application and the user specifications. The resulting structure would act as a pathway for obtaining the optimal architecture design option for multi objective optimization of the computing architecture used in many VLSI designs. The framework for optimization of computing architecture shown in this paper has been deduced and proved mathematically. The proposed method is capable to determine the most influential resource for a certain performance parameter in the whole system which is deduced by considering the mathematical model of the performance metric. The representation of our approach in the form of architecture tree allows easy automation of the process, useful for many multi objective optimized VLSI designs.

Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP)

As the growth of system complexity rapidly increases, the gap between Electronic System Level (ESL) and the Register Transfer Level (RTL) must be filled. Currently, Very Large Scale Integration (VLSI) and System-on-Chip (SoC) designs are multi-objective in nature, requiring simultaneous fulfillment of multiple parameters. Extensive research on Design Space Exploration (DSE) problems and synthesis of an application specific processor (ASP) design have been done until now but none of the prior works have focused explicitly on integrating a fast multi-objective architecture exploration mechanism with the architectural synthesis stages to formalize the design methodology of an application specific processor in case of multiple objectives. This paper proposes a design methodology of a multi-objective application specific processor by integrating an efficient multi-objective (area occupied, execution time and power consumption) exploration approach with the architecture synthesis process, useful for portable devices and many high end applications. The formalized steps of the design methodology for the ASP guarantees the designer an error free approach to design the system with strict limitations on compound operational constraints. The results of implementation of the designed ASP using the proposed design methodology in FPGA and ASIC have also been shown.

Hardware efficient design of speed optimized power stringent Application Specific Processor

New standards in communication, multimedia and signal processing have challenged the researchers to formalize the design methodology of an optimized Application Specific Processor (ASP) where the performance requirement should meet operational constraints like speed, chip area and power consumption. In this paper we describe a novel design approach to design a hardware efficient speed optimized power stringent application specific processor customized for a desired high performance. We initiate the design approach with the mathematical model of the application with strict operating constraints as specifications and finally describe our design at register transfer level. The proposed approach is capable for designing an ASP which is efficient not only in terms of hardware area but also contradictory parameters like speed and power consumption. To demonstrate our design approach for this power limited speed optimized ASP we selected a sample function as our application.

Rapid design space exploration for multi parametric optimization of VLSI designs

Design Space Exploration (DSE) is one of the most important stages in High Level Synthesis designing methodology. This paper presents a novel DSE approach for the current generation of systems with heterogeneous multi parametric optimization objectives. The method introduced in this paper is capable of concurrently resolving multiple conflicting issues encountered during DSE, such as maximization of accuracy needed in the evaluation of design space with minimization in time expended to explore the best architecture. Results of the proposed method for different benchmarks indicated significant acceleration in exploration process compared to another existing approach that is also based on Pareto optimal analysis.

Multi parametric optimized architectural synthesis of an application specific processor

Recent advancements in the field of multimedia and wireless communications have led to a wide array of application and services requiring high data processing rate at minimal power consumption. This new generation of data hungry portable devices requires power efficient hardware solutions where the operational specifications are as important as objective functionality. Conventional processing solutions like MIPS fall short on real time computational intensive operations due to large software overhead. This class of applications demands dedicated hardware units like Application Specific Processors (ASP) working as hardware accelerators for intensive data processing operations. In this paper we describe a novel Register Transfer Level (RTL) synthesis process of a power and throughput optimized ASP for a sample application. The ASP implemented on an FPGA, can serve as a hardware accelerator for system on chip (SOC) or as a standalone Application Specific Integrated Circuit (ASIC) at silicon level.