Anirudh Udupa

The cutting of metals via plastic buckling

The cutting of metals has long been described as occurring by laminar plastic flow. Here we show that for metals with large strain-hardening capacity, laminar flow mode is unstable and cutting instead occurs by plastic buckling of a thin surface layer. High speed in situ imaging confirms that the buckling results in a small bump on the surface which then evolves into a fold of large amplitude by rotation and stretching. The repeated occurrence of buckling and folding manifests itself at the mesoscopic scale as a new flow mode with significant vortex-like components—sinuous flow. The buckling model is validated by phenomenological observations of flow at the continuum level and microstructural characteristics of grain deformation and measurements of the folding. In addition to predicting the conditions for surface buckling, the model suggests various geometric flow control strategies that can be effectively implemented to promote laminar flow, and suppress sinuous flow in cutting, with implications for industrial manufacturing processes. The observations impinge on the foundations of metal cutting by pointing to the key role of stability of laminar flow in determining the mechanism of material removal, and the need to re-examine long-held notions of large strain deformation at surfaces.

Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias

Abstract Three-dimensional (3D) packages utilizing Through Silicon Vias (TSV) are seen as enablers of increased performance and “More than Moore” functionality. However, the use of TSVs introduce a new set of reliability concerns, one of which is the thermo-mechanical stress caused by the mismatch in coefficient of thermal expansion (CTE) between the copper via and the surrounding silicon. The CTE mismatch, causes high stress zones in and around the copper TSVs, which in turn impede the mobility of electrons in the regions surrounding the TSVs. Further, proximal placing of TSVs for improved electrical performance may be restricted by additional stress induced by TSV–TSV interaction. The increased stress of the region surrounding the TSV may also make the dielectric layers more prone to fracture. In order to ensure reliable functioning of 3D chip stacks, design guidelines are necessary on the excluded “keep-out” zone where stress induced by TSVs will impede transistor functionality. Ideally, these design guidelines are based on analytical stress solutions that are easy to incorporate within circuit design tools. Towards this end, we analytically derive, using elasticity theory, the stress field in and around a doubly periodic arrangement of TSVs subjected to a uniform thermal excursion. The solution is then extended to a “coated cylinder” model of TSVs in which the copper via is surrounded by an oxide layer, both of which are included in the silicon matrix. Finally, the model is extended to account for stress reduction caused by the onset of plasticity in the copper via.

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness

To obtain high yield for 3D ICs, random open defects, process variations, and thermal induced stress are key issues that must be addressed when synthesizing 3D clock networks. Current research on 3D clock synthesis often focuses on the construction and optimization of a 3D clock tree topology. Moreover, extra circuitry has been proposed to enable pre-bond testing and substitution of through silicon vias (TSVs) with random open defects. However, tree structures inherently have limited robustness to variations and may suffer failures arising from defects and/or process variations. To counter such problems, we propose to use TSVs to add redundancy in a 3D clock network. The proposed 3D network would have a complete 2D clock network on each die, facilitating pre-bond testing. Also, cross links would be inserted within each die using wires and across dies using TSVs to improve timing robustness within each die and across dies, respectively. Moreover, clock buffers are placed outside of zones that have high TSV-induced stress that could influence carrier mobility. Experimental results show that the proposed 3D clock networks have no failures due to random open defects, and on the average have 53% lower skew compared to 3D tree structures.

A framework for studying dynamics and stability of diffusive–reactive interfaces with application to Cu6Sn5 intermetallic compound growth

Often during phase growth, the rate of accretion, on the one hand, is determined by a competition between bulk diffusion and surface reaction rate. The morphology of the phase interface, on the other hand, is determined by an interplay between surface diffusivity and surface reaction rate. In this study, a framework to predict the growth and the morphology of an interface by modelling the interplay between bulk diffusion, surface reaction rate and surface diffusion is developed. The framework is demonstrated using the example of Cu–Sn intermetallic compound growth that is of significance to modern microelectronic assemblies. In particular, the dynamics and stability of the interface created when Cu and Sn react to form the compound Cu6Sn5 is explored. Prior experimental observations of the Cu6Sn5–Sn interface have shown it to possess either a scalloped, flat or needle-shaped morphology. Diffuse interface simulations are carried out to elucidate the mechanism behind the interface formation. The computational model accounts for the bulk diffusion of Cu through the intermetallic compound, reaction at the interface to form Cu6Sn5, surface diffusion of Cu6Sn5 along the interface and the influence of the electric current density in accelerating the bulk diffusion of Cu. A stability analysis is performed to identify the conditions under which the interface evolves into a flat, scalloped or needle-shaped structure.

Analysis of Interfacial Shear Stress and Risk of Debonding in TSVs

Through-Silicon Vias are a key enabler of 3D technology and reliability of these structures is a source of concern. TSVs are typically made of copper and therefore have a large CTE mismatch with the surrounding Si. When subjected to a thermal load during BEOL processing, they experience stress and deform. An important reliability concern that the stress poses is the debonding of the TSV-Si interface, and has been observed experimentally. A possible reason for the debonding is the high interfacial shear stress which could potentially be singular. The authors have obtained analytical estimates of the far-field stress and protrusion in a prior work. In this work the stress singularity at the tip of the TSV-Si interface is obtained. The order of the singularity is correlated to the risk of interfacial delamination.Copyright

A model for the free (top) surface deformation of through-silicon vias

Analytical models of stress and deformxation of through-silicon vias (TSV), relative to numerical ones, have the advantage of being inexpensive to evaluate and in providing insight. They have the additional advantage of allowing one to embed them in ECAD tools for real time design decisions. Motivated by this reasoning, in this paper, an analytical model for the three-dimensional state of stress in a periodic array of TSVs is developed. The model accounts for the onset of plasticity in the copper via and predicts the out-of-plane protrusion that occurs in the via due to differential thermal expansion with the surrounding Si matrix. Excessive out-of-plane deformation of the top surface of the via has the potential to induce fracture causing stress in the brittle dielectric layers that lie above the via. The predictions of the model are consistent with experimentally determined values reported in the literature. The process and design parameters that are critical to limiting the extent of protrusion are identified, and these in turn are used to develop design guidelines.