Anisul Haque

A comparison of wave-function penetration effects on gate capacitance in deep submicron n- and p-MOSFETs

We have calculated the effects of wave function penetration into the gate-oxide on the modeling of gate capacitance in deep submicron p-MOSFETs on [100] silicon for the first time. These results are compared to those of n-MOSFETs. Self-consistent calculations show that contrary to the common belief, penetration effects are more pronounced in p-MOS devices. The error in inversion capacitance due to neglect of penetration effects has opposite dependence on substrate doping density for n-MOS and p-MOS structures. Consequently, the error in gate capacitance for an n-MOSFET in strong inversion is strongly dependent on doping density, while that for a p-MOSFET essentially does not depend on doping density. An explanation for this unusual result is also provided. Although the error in gate capacitance is only a few percent, it will have nontrivial effects on device parameter extraction from capacitance-voltage (C-V) measurements.

Electronic band structures of GaInAsP/InP vertically stacked multiple quantum wires with strain-compensating barriers

Energy-band structures of compressively strained GaInAsP/InP quantum wires fabricated by etching and regrowth method have been calculated using an 8 band k⋅p theory including strain relaxation. The effects of strain-compensating barriers and vertically stacking multiple wire layers on band structures are investigated. It is found that due to the dependence of strain relaxation on the amount of strain compensation in barrier regions and on the number of wire layers in the vertical stack, unlike strained quantum films, the energy-band structures of strained quantum wires are dependent on these factors. Experimentally observed wire-width dependence of the large energy blueshift in vertically stacked multiple quantum-wire structures is accurately explained using our calculations without any fitting parameter. Additional broadening in the emission spectra due to vertically stacking multiple quantum wires is found to be negligible. Our results show that strain compensation in barrier layers may be used effectiv...

GaInAsP/InP Partially Strain-Compensated Multiple-Quantum-Wire Lasers Fabricated by Dry Etching and Regrowth Processes

This paper reports the structural properties and lasing characteristics of GaInAsP/InP multiple-quantum-wire lasers fabricated by electron beam lithography, CH4/H2-reactive ion etching and organometallic vapor-phase-epitaxial regrowth. Good size distributions of multiple-quantum-wire structures (wire widths of 18 nm and 27 nm in a period of 80 nm) have been obtained with standard deviations less than ±2 nm. We have confirmed that low-damage etched/regrown interfaces of quantum-wire structures can be realized by using a partially strain-compensated quantum-well structure. Threshold current densities of 5-quantum-well wirelike lasers (wire widths of 43 nm and 70 nm) were found to be lower than that of the quantum-film laser, fabricated from the same initial wafer, due to a volume effect at temperatures up to 85°C. Finally, room temperature (RT)-continuous wave (CW) operation of multiple-quantum-wire lasers (wire width of 23 nm in a period of 80 nm, 5-stacked quantum-wires) was achieved, and the good reliability of this quantum-wire laser was demonstrated for the first time by means of lifetime measurement under the RT-CW condition.

An efficient technique to calculate the normalized wave functions in arbitrary one-dimensional quantum well structures

We present a simple yet unified technique to calculate: (i) the eigenenergies and the normalized eigenstates in quantum wells, (ii) the energy broadened spatially varying density-of-states in leaky quantum wells where the particle lifetime is finite, and (iii) the energy position dependent density-of-states in quantum wells where phase-breaking and/or inelastic scattering processes are present. The method is based on the Green’s function formalism. The method is particularly attractive in numerical calculations of multibarrier devices in which the estimation of the self-consistent potential is desired.

On the Enhancement of the Drain Current in Indium-Rich InGaAs Surface-Channel MOSFETs

The effects of interface-trap states (<i>D</i>_it) and the shift of the charge neutrality level (CNL) on the enhancement of the drain current in In-rich surface-channel enhancement-mode n-type InGaAs MOSFETs are investigated. In addition to the increase in the bulk mobility, the shift of the CNL toward the conduction band together with high densities of <i>D</i>_it is responsible for the experimentally observed remarkable enhancement of the on-state drain current with increasing In content in the channel. However, when <i>D</i>_it is low, current enhancement is weak, and the location of the CNL has little effect on the current enhancement. Acceptor-type interface-trap states above the conduction-band minima (CBM) play an important role in determining the inversion-layer electron mobility. Representing <i>D</i>_it distribution above the CBM by a constant equal to the <i>D</i>_it value at the CNL causes an overestimation of the drain current at higher gate voltages. It is also observed that the extraction of <i>D</i>_it from the low-frequency gate <i>C</i>-<i>V</i> data is independent of the location of the CNL. We further show that the subthreshold slope (SS) is doubled due to <i>D</i>_it. However, the location of the CNL or the magnitude of <i>D</i>_it above the CBM has little effect on the SS.

Accurate modeling of direct tunneling hole current in p-metal–oxide–semiconductor devices

We critically examine a number of important issues related to modeling hole direct tunneling in p-metal–oxide–semiconductor devices with p+-polycrystalline silicon gate. By comparing our simulated direct tunneling hole current with experimental data, several observations are made. It is found that inelastic trap scattering of holes in the gate-oxide region increases the hole tunneling current significantly at lower gate voltages in devices with gate-oxide thickness greater than 2 nm. Appropriate spatial and gate bias dependence of the scattering rate needs to be considered for accurately predicting experimental current over the entire gate voltage range. Effective mass of holes in gate-oxide region is not a constant, rather, it increases with increasing gate bias voltage and we propose a relationship between the two. Bulk values for hole effective masses in silicon may be used to accurately model the hole tunneling current even in the presence of hole quantization. The contribution of split-off holes to d...

Quantum transport in mesoscopic devices: Current conduction in quantum wire structures

A theory based on the Keldysh formalism is developed to study carrier transport in inhomogeneous quantum effects devices that operate at higher temperatures under large applied bias voltages. The scattering rates due to dissipative processes within devices are estimated self-consistently from the nonequilibrium particle density and the density of states. Unlike many existing models, the present model guarantees the conservation of the current and the number of particles in active devices. We have applied our model to study carrier transport in GaAs quantum wire devices and report several interesting results. It is found that a sudden increase in the polar-optical phonon scattering rates may result in a negative current at some critical energies when the bias voltage is positive. At low temperatures, the conductance of quantum wires shows quantized steps as a function of the applied bias voltage. Moreover, a negative differential conductance (NDC) is observed in the current–voltage characteristics of devic...

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.

Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs

Direct tunneling gate current in MOS structures with ultra-thin gate-oxides in the presence of inelastic scattering in oxide region is studied using a new technique. Numerically calculated results for nMOS devices show that due to inelastic scattering, gate current increases in devices with oxide thickness equal to 2 nm or higher. Inelastic scattering effects are more pronounced at lower gate voltages. However, when the oxide thickness is reduced below 2 nm, inelastic scattering has no significant effect on gate current.

Room Temperature-Continuous Wave Operation of GaInAsP/InP Multiple-Quantum-Wire Lasers by Dry Etching and Regrowth Method

Room temperature (RT)-continuous wave (CW) operation of GaInAsP/InP quantum-wire lasers fabricated by electron beam lithography, CH4/H2-reactive ion etching and organometallic vapor-phase-epitaxial regrowth was realized for the first time. The threshold current density of 802 A/cm2 and differential quantum efficiency of 36% were obtained for a device with strain-compensated 5-layered quantum-wires with the wire width of 23 nm in the period of 80 nm, the stripe width of 15 µm and the cavity length of 1.15 mm. From lifetime measurement under RT-CW condition, no noticeable degradation in light output was observed even after more than 3,200 h.