Anjan Bhattacharyya

Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices

Abstract A theoretical model is developed to characterise the write, erase and charge retention mechanisms of floating gate EEPROM devices. The model depicts the effect of the properties of thin tunnel oxide, interpoly oxide, injector area, and programming voltage on the device performance. The effect of trapping of electrons in the thin oxide during repeated write/erase cycles is also described.

Si/SiO2 interface roughness: Structural observations and electrical consequences

Thin oxides (on the order of 80–90 A) grown at 900 °C in dry O2 diluted with Ar were examined in cross section by high‐resolution transmission electron microscopy. Varying degrees of roughness at the substrate/oxide interface were observed, depending on the processing sequence employed. Nonuniformity of the interface was found to correlate with undesirable electrical characteristics. By adding an intermediate annealing step to the oxidation process, the quality of the film was greatly improved. A qualitative model for the observed behavior based on stress effects and viscous flow considerations is presented.

Study of reactive‐ion‐etch‐induced lattice damage in silicon by Ar, CF4, NF3, and CHF3 plasmas

Reactive‐ion‐etch‐induced damage in silicon has been investigated using transmission electron microscopy (TEM), Rutherford backscattering (RBS) ion channeling, and laser‐induced thermal waves (TW). A correlation has been found between lattice damage in silicon due to reactive ion etching and leakage current properties of thermal oxide films subsequently grown on the damaged silicon. The silicon wafers were plasma etched using Ar, CF4, NF3, and CHF3 etch gases at dc bias voltages ranging from 150 V to 450 V. Lattice damage at the silicon surface, as determined by TEM and RBS, was found to depend on both the dc bias voltage and the etch chemistry. Subsequent leakage current measurements of the silicon oxides show that the samples with more silicon substrate lattice damage prior to oxidation also have correspondingly higher leakage. The thermal wave technique also indicates a damage dependence on dc bias and on etch chemistry; however, the thermal wave measurements indicate a damage dependence on etch chemistry different from TEM and RBS measurements. The source of this difference is not yet understood.

Analysis of MOSFET degradation due to hot-electron stress in terms of interface-state and fixed-charge generation

Abstract An analysis of MOSFET degradation induced by hot-electron stress is carried out by separating the effects of generated fixed-oxide charge ΔQF, due to trapped electrons in the gate oxide and charge in the generated interface states ΔQi. Both influences are considered in the subthreshold and above-threshold bias regions using a model for the stressed device which divides its channel into two regions having different threshold voltages. A phyiscal explanation is offered for degradation of transconductance gm by considering the VG dependence of the charge in the interface states ΔQi and the threshold voltage VT. It is predicted that an increase in QF alone causes the magnitude of the threshold voltage VT to increase and the device turn-on to become more abrupt (transconductance gm increases), while an increase in Qi alone results in a softer turn-on (gm decreases) and makes the threshold voltage dependent on VG. The generated interface state density Dit and the fixed charge density ΔQF is extracted by fitting the measurements to the above threshold ID-VG characteristics (small drain voltages) calculated with the model. Furthermore, we find that while both QF and Qi increase monotonically with stress, the contribution of ΔQi to the change in VT is significantly larger than that due to the change in QF. This conclusion is independent of stress time or of the exact division of the channel (the assumed lengths L1 and L2). Interface state densities obtained from the measured slopes of subthreshold ID-VG plots (which are affected by states near the middle of the band gap) are appreciably lower than densities deduced from measurements made above threshold (which are sensitive to states near the band edges) using the divided-channel representation. An increased dependence of subthreshold current on VD after stress is attributed to short-channel behavior of the MOSFET in the vicinity of the drain. The effects of hot-carrier stress in p-channel MOSFETS are also interpreted in terms of the two-transistor representation.

Effect of addition of TCA (trichloroethane) on the electrical properties of thin oxides processed by a two-step oxidation technique

The authors have investigated the combined effect of the addition of TCA (trichloroethane) and an intermediate annealing step to reduce the density of defects that develop in thin oxides during the oxidation process. Thin oxides (85-95 AA) were grown at 950 degrees C in dry O2 with varying amounts of Ar dilution and with or without TCA. Oxide breakdown voltage, current against voltage (Fowler-Nordheim parameters) and both high-frequency and quasi-static capacitance against voltage measurements were used to characterise the electrical properties of thin oxides. They show that the addition of TCA is most effective in improving the electrical properties of thin oxides when combined with an intermediate annealing step.

Effect of trapping in thin oxides on the write and erase characteristics of floating gate EEPROM devices

For EEPROM devices, it is typically observed that the threshold window, defined as the difference between the erase and write threshold voltage, begins to narrow gradually until around 106 cycles when the window collapses. This phenomenon of window collapse can be attributed to trapping of injected electrons in the thin tunnel oxide. The authors present a calculation which demonstrates the effect of electron trapping on window collapse.

Influence of diffusion of hot carriers on collection efficiency of solar cells:a-Si:H

The author has considered the effects of the optically generated hot carriers to explain the decrease in collection efficiency of solar cells at short wavelengths. The diffusion of these hot carriers to a contact or interface before thermalisation is the major factor for reduction of collection efficiency.