Anna Antola

High-level synthesis of data paths with concurrent error detection

High-level synthesis of data paths with concurrent self-checking abilities is discussed to balance redundancy, latency, and checking effectiveness. The nominal and the checking computations are scheduled and allocated contemporaneously by using a force-directed approach to limit the number of redundant units required to achieve detection within the latency of the nominal computation only. Resource sharing between the nominal and the checking computation is used to minimise the redundancy, while keeping error aliasing as reduced as possible.

A Novel Hardware/Software Codesign Methodology Based on Dynamic Reconfiguration with Impulse C and Codeveloper

The design of embedded systems has rapidly changed during the last decade. It is possible to identify two main responsible factors: hardware/software codesign and dynamic reconfiguration. The work presented in this paper tries to investigate how to consider the reconfiguration as an explicit dimension in the design flow for embedded systems. This work addresses the challenge introduced by the partial dynamic reconfiguration trying to propose a novel design flow, using the CoDeveloper framework to speedup the design process. The proposed flow allows the designer to define his/her desired specification using an high level design language such as C. Finally, it provides results showing how the proposed flow can be used by the designer to have more information useful in making the correct decisions during the design of his/her embedded system.

Semiconcurrent error detection in data paths

A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. Attention is mainly focused on data path design. After identifying the reference architecture against which cost and performance are evaluated, a simultaneous scheduling-and-allocation strategy is presented for linear-code data flow graphs, allowing resource sharing between nominal and checking data paths. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm since it is essentially concerned with the introduction of the fault tolerance issue at high-abstraction level in any design environment. Conventional duplication with comparison, even if considered in a high-level synthesis strategy, leads to high circuit complexity increase. The proposed approach provides that the required checking periodicity is satisfied while minimizing additional functional units by means of maximum reuse of the resources available for the nominal computation as long as error detection ability is preserved. The strategy is then extended to deal with branches and loops in the data path. Risk of error aliasing due to resource sharing is analyzed.

On-line diagnosis and reconfiguration of FPGA systems

Fault tolerance is becoming an important issue for the effective use of FPGA-based architectures in mission-critical applications. This paper introduces an innovative approach to design FPGA systems with on-line diagnosis and reconfiguration, at a limited cost in terms of FPGA redundant resources and interconnections. The technique is based on high-level synthesis of the self-checking datapath to be mapped on the FPGA. The analysis of the computation flow allows for location of the necessary checking points. Scheduling is performed in order to minimize the circuit complexity, while satisfying the maximum latency allowed by the application. Allocation is performed as a suited trade-off between the circuit complexity and the reconfiguration efficiency. Problems and constraints due to re-use of units in different points of the computation are taken into account. The faulty block replacement policy is discussed, together with its implication in terms of re-use and of interconnection re-routing.

Fault-tolerance in FFT arrays: time-redundancy approaches

Fault tolerance in VLSI/WSI FFT arrays acquires relevance when defects and run-time faults become significant, due to large dimensions of processors and arrays. Then, both restructuring to overcome end-of-production defects and reconfiguration to overcome run-time faults are required, to achieve the dual purposes of higher yield and higher reliability.Adopting as basic FFT network the two-dimensions array that directly corresponds to the FFT flow graph, the usual structure redundancy techniques tailored for two-dimensions arrays reconfiguration are not well applicable, since the limited locality of this network leads to relevant area increase due to the augmented interconnection structure.In this paper,time redundancy is suggested as a viable alternative for the two-dimensions FFT array; two different solutions are presented, one based oninter-stage reconfiguration, the other one adoptingintra-state reconfiguration, both allowing for survival to multiple faults with limited increase of network complexity and very small hard-core sections. As usual in many time redundancy methods, both approaches result in a processing speed equal to half the processing speed granted by an ideal, fault-free device.Reliability and survival ratios to multiple faults are evaluated for the two cases, taking into account also the area increments necessary for fault tolerance. The reliability evaluations allow for a direct comparison of the two solutions.

A high-level synthesis approach to optimum design of self-checking circuits

We present an innovative solution to design of self checking systems implementing arithmetic algorithms. Rather than substituting self checking units in system synthesized independently of self checking requirements, we introduce self checking in high level synthesis as a requirement already for scheduling the DFG. Rules granting error detection allow optimum partitioning of the DFG; minimum latency, resource constrained scheduling is performed with the support of such partitioning so as to optimize the number of checkers as well as that of other resources.

Optimising high-level synthesis for self-checking arithmetic circuits

Introduction of self-checking capacity in arithmetic systems since the initial steps of high-level synthesis is taken into account, as an alternative to conventional solutions that adopt ad-hoc coding or comparable techniques after the register-level architecture has been fully defined. A technique based on initial partitioning of the Data Flow Graph into detectable subgraphs is proposed, by which all single errors appearing within one subgraph are detected; an algorithm leading to optimize resource sharing (allocation and binding of both functional units and registers) while keeping minimum latency and optimum number of checkers is discussed.

Testing and diagnosis ofFFT arrays

The problem of testing and diagnosing dedicated architectures directly derived from an algorithmic flow is here considered. The main scope is that of defining a procedure allowing complete fault coverage (within a specified fault model) and-possibly-non-ambiguous fault location for such architectures. Information required is limited to the structure of the algorithmic flow and to a functional description of the architectures building blocks; no further control and observation points are inserted and no detailed knowledge of the internal structure of the building blocks is required. In correspondence, functional error models are defined. The case study examined here is that of radix-2FFT graphs. It will be proved that a one-pass testing procedure allows detection of all single faults and location-without ambiguity-to the corresponding equivalence class. It will also be proved that the procedure requiresO(N) operations for anN-point array. In the case of multiple faults, fault coverage is still granted but non-ambiguous fault location is in general not possible.

A low-redundancy approach to semi-concurrent error detection in data paths

A high-level synthesis approach is proposed for the design of semi-concurrently self-checking devices; attention is focused on data path design. After identifying the reference architecture against which cost and performances should be evaluated, a simultaneous scheduling-and-allocation algorithm is presented, allowing resource sharing between nominal and checking data paths. The algorithm grants that the required checking periodicity is satisfied while minimizing additional costs in terms of functional units. Risk of error aliasing due to resource sharing is analysed.

Policies for fault-tolerance through mixed space- and time-redundancy in semi-systolic FFT arrays

Fault-tolerance in semisystolic FFT (fast Fourier transform) arrays is considered, with the primary aim of obtaining either end-of-production restructuring or offline reconfiguration at run-time. A mixed-mode solution is proposed, limiting the amount of structure redundancy, keeping intact nominal processing speed, more complex fault distributions require use of time-redundancy, whereby nominal speed decreases but processing power is kept unchanged. The modified architecture granting such performances is presented, and the percentage of survival to faults thus achieved is evaluated. Reliability is assessed by evaluation of the weighted probability of survival for the fault-tolerant structure related to the number of present faults.<<ETX>>