Anshu Gaur

Printed thin-film transistors and complementary logic gates that use polymer-coated single-walled carbon nanotube networks

This paper reports on the electrical properties of thin-film transistors (TFTs) that use polymer-coated networks of single-walled carbon nanotubes (SWNTs) as the semiconductor with source and drain electrodes formed by high-resolution printing techniques. P-channel, n-channel, and ambipolar TFTs are demonstrated with bare SWNT networks, networks coated with polyethylene imine and with polyethylene oxide, respectively. Studies of the scaling of properties with channel length and tube density reveal important information about the operation of these devices. Complementary inverters made with n- and p-channel devices show gain larger than one and illustrate the potential use of these types of TFTs for complex logic circuits.

Processing dependent behavior of soft imprint lithography on the 1-10-nm scale

This paper examines aspects of a soft nanoimprint lithography technique for operation at resolutions that approach the 1-nm regime. Systematic studies using polymer molds made with single walled carbon nanotubes (diameters between 0.5 and 5 nm) and high-resolution electron beam patterned layers of hydrogen silsesquioxane (line widths and heights /spl sim/10 and 20 nm, respectively) as templates reveal a dependence of the resolution limits on the polymer processing conditions. In particular, using a single choice of polymers for the molds and the molded materials, imprint results show that the conditions for spin casting and curing the polymers determine, to a large degree, the resolution and replication fidelity that can be achieved. Optimized procedures enable imprinted polymer surfaces that have a root mean squared surface roughness of /spl sim/0.26 nm or lower and a resolution as high as /spl sim/1 nm. These characteristics are significantly better than previous results obtained using these same polymers with unoptimized conditions. A diversity of molded polymers, including Bisphenol-F epoxy resin, polyacrylic acid, and polyurethane, show similar high-fidelity imprinting capabilities. Different procedures enable accurate relief replication for features with modest aspect ratios and dimensions of /spl sim/10 nm. The results indicate that choice of processing conditions is, in addition to materials selections, extremely important in achieving high-fidelity soft nanoimprint lithography in the 1-10-nm regime.

Selective growth of InAs quantum dots by metalorganic chemical vapor deposition

We report results of both strain-driven surface segregation of indium from InGaAs thin films as well as selective area epitaxy of InAs quantum dots using these films. InAs segregation from an underlying InGaAs film allows for preferential growth of quantum dots when additional InAs is deposited. By using standard lithography techniques, a two-step selective growth process for quantum dots is achieved. Furthermore, by utilizing self-assembled nanostructures as a template, selective growth of coalesced wires and dots with 100-nm feature sizes are realized.

Nano on nano

Selective epitaxy of quantum dots using self-assembled segregation promises nanoscale resolution at conventional lithography prices.

Role of temperature gradients in blanket tungsten for microelectronic contacts

A tungsten plug process is commonly employed in microelectronic interconnect technology. This paper provides a review of the relative advantages of the two variants - blanket and selective tungsten-and subsequently focuses on the former. Specifically, we address the role of thermal gradient that may naturally occur or be intentionally applied during blanket tungsten deposition, whereas most published literature examines the isothermal process. We present a one-dimensional mass transport and deposition model for a cylindrical contact hole/via. In the numerical calculations, a temperature gradient is imposed on a via hole such that its bottom is slightly hotter than the mouth from which the deposition gases enter. We find that the tendency to form a keyhole void diminishes when a temperature gradient is present, as compared to the isothermal process at a temperature corresponding to that either at the mouth or pore bottom. Furthermore, the extent of gain due to a thermal gradient depends on the temperature level; the advantage is greater at higher levels. However, in practical applications, the thermal conductivity of the dielectric layer in which the contact hole is formed should be low in order to achieve the required gradient. This aspect should also be kept in mind when searching for new materials with low dielectric constant.

BLANKET TUNGSTEN: A NON-ISOTHERMAL APPROACH

The metal in the blanket tungsten process for microelectronic interconnects is deposited in via holes or trenches of sub-micron radius/width and depths of the order 2 μm. This process is usually isothermal, based on chemical vapor deposition. However, the resulting concentration gradients along the depth of the via promote formation of a void (keyhole) in the feature, unless processing is at low temperatures and hence, for longer duration. Using process modeling, the feasibility of the two approaches are investigated that rely on a non-isothermal process, which are equally fast and reduces the volume of the keyhole defect. In the first, application of a thermal gradient is examined, which can mitigate the tendency to form keyholes. However, the process conditions require excessive gas flow rates. In another, continuous cooling of the substrate while deposition occurs simultaneously is examined. The method based on continuous cooling appears more feasible in optimizing between keyhole size and process time.