Anshul Kumar

ASIP design methodologies: survey and issues

Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the art in this area and identifies some issues which need to be addressed. We have identified the five key steps in ASIP design as application analysis, architectural design space exploration, instruction set generation, code synthesis and hardware synthesis. A broad classification of the approaches reported in the literature is done. The paper notes the need to broaden the architectural space being explored and to tightly couple the various subtasks in ASIP synthesis.

Battery model for embedded systems

This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It then throws new light on the battery recovery behavior, which can help determine optimum discharge profiles and hence result in significant improvement in battery lifetime. Finally it proposes a fast and accurate stochastic model which draws the positives from the earlier models and minimizes the drawbacks. The parameters for this model are determined by a pretest, which takes into account the newfound background into recovery and rate capacity hence resulting in higher accuracy. Simulations conducted suggest close correspondence with experimental results and a maximum error of 2.65%.

Strap-down Pedestrian Dead-Reckoning system

This paper presents a waist-worn Pedestrian Dead Reckoning (PDR) System that requires minimal end-user calibration. The PDR system is based on an Inertial Measurement Unit (IMU) comprising of a tri-axial accelerometer, a tri-axial magnetometer and a tri-axial gyroscope. We propose a novel heading estimation scheme using a quaternion-based extended Kalman filter (EKF) that estimates magnetic disturbances and corrects for them. Accelerometer measurements are used to detect step events and to estimate step lengths. Experimental results show that a relative distance error of about 3% to 8% can be obtained using our methods.

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to support FU requirements, which makes them expensive and extremely slow. A simple solution is to break the register file into a number of smaller register files with a subset of FUs connected to it. These architectures are termed clustered VLIW processors. In this article, we first build a case for clustered VLIW processors with four or more clusters by showing that the achievable ILP in most of the media applications for a 16 ALU and 8 LD/ST VLIW processor is around 20. We then provide a classification of the intercluster interconnection design space, and show that a large part of this design space is currently unexplored. Next, using our performance evaluation methodology, we evaluate a subset of this design space and show that the most commonly used type of interconnection, RF-to-RF, fails to meet achievable performance by a large factor, while certain other types of interconnections can lower this gap considerably. We also establish that this behavior is heavily application dependent, emphasizing the importance of application-specific architecture exploration. We also present results about the statistical behavior of these different architectures by varying the number of clusters in our framework from 4 to 16. These results clearly show the advantages of one specific architecture over others. Finally, based on our results, we propose a new interconnection network, which should lower this performance gap.

Grammar-based hardware synthesis of data communication protocols

For a synthesis methodology to support implementation independent design specification, a capability for design space exploration is essential. In this paper we present such a methodology for a specific domain: data communication protocols. A natural way to specify various elements of protocols is in terms of a grammar annotated with actions. Our language for protocol specification, called PRO-GRAM, is based on this idea. The hardware specification of the protocol is done by specifying the bit-patterns of the tokens the protocol is supposed to parse together with the actual grammar to parse the input stream. By specifying constraints on the input and output stream ports, the designer is allowed to explore alternative realisations with different widths of the I/O ports. The PRO-GRAM compiler outputs VHDL-code suitable for logic synthesis.

Automatic synthesis of system on chip multiprocessor architectures for process networks

We present an approach for automatic synthesis of system on chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.

Application Specific Datapath Extension with Distributed I/O Functional Units

Performance of an application can be improved through augmenting the processor with application specific functional units (AFUs). Usually a cluster of operations identified from the application forms the behavior of an AFU. Several researchers studied the impact of input and output (I/O) constraints for a legal operation cluster on the overall achievable speedup. The general observation is that the speedup potential grows with the relaxation of I/O constraints. Going further, in this paper, the authors investigate the speedup potential of AFUs in the absence of I/O constraints. Design challenge in the absence of I/O constraints is addressed in a very practical manner, through the identification of maximal convex subgraphs. Usually the available register ports are few but the number of inputs/outputs of the identified patterns are likely to be large. The authors solve the register port limitation by the design of distributed I/O functional units, in which the operands are communicated in multiple cycles. The experimental results show that selection of maximal clusters achieves average 50% higher speedup than selecting I/O constrained operation clusters. Also, our identification algorithm runs 2 to 3 orders faster than an exhaustive identification approach

A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units

It is widely accepted that use of an Application Specific Instruction Set Processor (ASIP) in an embedded system can provide a solution which is much more flexible than ASICs and much more efficient than standard processors in terms of performance and power consumption. However a lack of an acceptable design methodology and supporting tools for ASIPs limits their use even today. We present in this paper a methodology for design space exploration of high performance VLIW ASIPs by modeling Application Specific Functional Units in Trimaran Compiler Infrastructure. To demonstrate the effectiveness of our strategy we consider two important applications FFT and Kalman Filter and perform compute intensive operations in these applications via special Functional Units. The results we obtain are very promising with up to 2/spl times/ speed improvement.

A high-level synthesis flow for custom instruction set extensions for application-specific processors

Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality.

Automatic Generation of Digital System Schematic Diagrams

This paper presents a rigorours approach to automatic generation of schematic diagrams for digital systems described as networks of modules. This is very useful in comprehensive CAD environment. The approach is based on identification of some guidelines which are traditionally followed in mannual drawing of schematic diagrams. Theses guidelines are transformed into quantitative objectives. In view of the complex interrelationship between these objectives, the schematic design process is broken into a long sequence of steps. An attempt is made to give rigorous formulation for each step, along with efficient solutions, making suitable approximations where necessary. An illustrative diagram generated using these algorithms is included showing that the results compare well with hand drawn diagrams.