Anthony L. Chun

Architecture of the Scalable Communications Core

The scalable communications core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based 3-ary 2-cube network on chip (NoC). The combination of the accelerators, which were developed for key communications operations, and the NoC results in an architecture that is flexible for multiple protocols, extensible for future standards and scalable to support multiple simultaneous streams

Key lessons from the scalable communications core: a reconfigurable wireless baseband

The radios in mobile Internet devices and smart phones need to support a wide range of wireless standards for cellular, broadband, local, and personal area network connectivity, satellite navigation, and broadcast digital television in a small form factor with low energy consumption. The customary approach is to integrate an optimized antenna, front-end, baseband, and MAC for each protocol; however, any upgrades or modifications for new or different product definitions require a costly respin of the silicon. An alternative approach is to integrate flexible components including an antenna, front-end, baseband, and MAC into a radio that enables one set of hardware to satisfy multiple protocols and also provides scalability for protocol changes in the future; however, there is a penalty in terms of area and power that has to be considered. An example of a flexible baseband is the Scalable Communications Core. This core was developed by Intel Labs and consists of a heterogeneous set of coarse-grained programmable accelerators connected via a packet-based network-on-chip. To understand the area and power cost of the architecture, we taped out a prototype SCC test chip in a 65 nm CMOS process, and programmed and validated it for multiple protocols, including WiFi, WiMAX, GPS, Bluetooth, and DVB-H. This article summarizes our key results in architecture, programming, interconnection, and performance of a flexible baseband for realtime wireless communications applications.

ISIS: An accelerator for Sphinx speech recognition

The ability to naturally interact with devices is becoming increasingly important. Speech recognition is one well-known solution to provide easy, hands-free user-device interaction. However, speech recognition has significant computation and memory bandwidth requirements, making it challenging to offer at high performance, real-time and ultra-low power for handheld devices. In this paper, we present a speech recognition accelerator called ISIS. We show the overall execution flow of the accelerated speech recognition solution along with optimizations and the key metrics of performance, area and power.

Overview of the Scalable Communications Core

The scalable communications core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-switched 3-ary 2-cube network on chip (NoC). The combination of the accelerators, which were developed for key communications kernels, and the NoC results in an architecture that is flexible for multiple protocols, extensible for future standards and scalable to support multiple simultaneous streams.

Channel-adaptive complex K-best MIMO detection using lattice reduction

Lattice reduction (LR) aided detectors mitigate the exponentially increasing complexity of large multiple-input, multiple-output (MIMO) systems while achieving near-optimal performance with low computational complexity. In this paper, a channel-adaptive complex-domain LR-aided K-best MIMO detector is presented that reduces the gap between the K-best sphere decoding (SD) detector and the maximum likelihood (ML) optimal MIMO detector. While maintaining BER performance, computational complexity is reduced by 50% over a conventional complex domain K-best SD detector by implementing a new on-demand complex-domain candidate symbol selection algorithm. Two tunable variables in the candidate selection process are introduced to enable both coarse-grained and fine-grained adaptation of computational complexity to channel conditions.

GRoM — Generalized robust multichannel featur detector

A number of well-known computer vision algorithms for image feature detection use luminosity only or some specific color model. Although these methods are effective in many cases, it can be shown that these transformations of the full image information reduce detection performance due to method-induced restrictions. In this paper, we describe a formal approach to the construction of a multi-channel interest point detector for an arbitrary number of channels (regardless of data nature), which maximizes the benefits from the usage of information from these additional channels. We introduce the Generalized Robust Multi-channel (GRoM) feature detector prototype that is based upon the proposed approach, detail features of GRoM and include a set of illustrative examples to highlight its differentiation from existing methods.

Application of the Intel/sup /spl reg// reconfigurable communications architecture to 802.11a, 3G and 4G standards

The increasing number of wireless LAN, MAN, PAN and WAN standards creates challenges for wireless equipment manufacturers: support multiple protocols in a multimode radio, reduce time to market for adding new capability for new standards, and keeping up with the ever increasing data rates that are required. One solution to these challenges is the Intel/sup /spl reg// reconfigurable communications architecture (RCA). RCA is a power and area efficient design for physical layer (PHY) and lower MAC processing. To achieve the desired efficiency for multiprotocol processing, we defined several programmable accelerators for key communications operations. This work describes our analysis of mapping various wireless protocols (WLAN, 3G and a proposed 4G standard) to RCA. These results indicate that our architecture has enough flexibility and scalability to support a range of standards.

Application of the Scalable Communications Core as an SDR Baseband

Today’s consumers expect the connectivity of data anywhere and at anytime, i.e., voice and media for their smartphones, notebooks, and tablets. They also aspire that their wireless devices be small with a long battery time and life. To meet the first requirement, a smartphone must support a large number of radio standards; this has motivated the development of Flexible Radios that efficiently support a wide range of wireless communication standards. In this context, adaptive radios modify their performance based on the environment. The Cognitive Radios sense the RF environment to use available spectrum and standards. A key enabling technology for each of these types of radios is Software Defined Radios (SDR) that support numerous current and future standards, share resources between different radio threads, and dynamically add new radio threads to an operational radio. The SDR architecture must also be both area- and energy-efficient. One example of an efficient and flexible baseband architecture is the Scalable Communications Core (SCC), which was developed by Intel Labs and meets many of the requirements for an SDR baseband, including programmability, resource sharing, and efficient scheduling of radio threads. Consisting of a heterogeneous set of coarse-grained, programmable accelerators connected via a packet-based Network-on-Chip (NoC), the resulting architecture is energy- and area-efficient. We taped out a prototype SCC test chip in a 65 nm CMOS process, programmed and validated it for multiple protocols, including WiFi, WiMAX, GPS, Bluetooth, and DVB-H and found that its measured energy and area efficiency were competitive with other flexible baseband architectures.