Anthony S. Wojcik

A general constructive approach to fault-tolerant design using redundancy

The use of redundancy to attain a fault-tolerant system design is described. Specifically, a general theory of redundancy is proposed that allows the design of fault-tolerant structures at the system-level, gate-level, or both. The theory accounts for classic approaches to redundant design such as TMR, NMR, and quadded and interwoven logics. It is shown that, by using mathematical block theory, it is possible to describe complex interconnections of redundant elements in a simple, straightforward fashion. Comparisons are made with other approaches to redundant design. >

Formal verification of fault tolerance using theorem-proving techniques

A formal verification system based on the use of automated reasoning techniques is described to validate fault tolerance. An extended Petri net representation, called a flow net, is described together with the theorem-proving implementation of a rule-based system for manipulating system descriptions. Examples taken from the literature are used to illustrate the representation and the capabilities of the formal verification system under development. >

Identifying high-level components in combinational circuits

The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer-aided design. Existing techniques rely upon finding exact matchings of subcircuit structure within the layout. These syntactic techniques fail to identify functionally equivalent subcircuits which are differently implemented optimized, or otherwise obfuscated. We present a mechanism for identifying functionally equivalent subcircuits which is capable of overcoming many of these limitations. Such semantic matching is particularly useful in the field of design recovery.

A Rule-Based Circuit Representation for Automated CMOS Design and Verification

A novel rule-based circuit representation is proposed to describe the connectivities of CMOS circuits at the transistor level. The unique feature of the rule-based representation is its ability to automate CMOS circuit design and verification. A precise symbolic description of the functionality of a transistor-level circuit can be derived based on a set of production rules in linear time. Automated synthesis and verification of CMOS logic circuits are demonstrated.

Candidate subcircuits for functional module identification in logic circuits

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

Modular decomposition of combinatorial multiple-values circuits

A decomposition approach to the modular design of multiple-valued logic functions is discussed. Systematic procedures to utilize a fixed set of building blocks from which an arbitrary function can be designed are illustrated. The building blocks are composed of T gates (multiplexers). The first step is the partitioning of all logic functions into classes. Representative building blocks for each class are then developed. Finally, optimization techniques are described that reduce the number of building blocks required in the design. This approach is, in principle, applicable to functions in any radix and will always yield a design for the target function. Examples are presented to illustrate the approach for ternary functions. >

Efficient algorithms for subcircuit enumeration and classification for the module identification problem

The problem of extracting RTL modules from a gate level netlist has many interesting applications in digital design (V.K. Madiseti, 1999; P. Schaumont et al., 1999; K. Singh and P. Subrahmunyam, 1995), because it provides a conceptual description of the circuit. We approach this transformation by solving two subproblems: the identification of potential modules (candidate subcircuits) and testing them for functional equivalence to known high-level modules (subcircuit identification). We present a technique for unique and comprehensive enumeration of subgraphs of an arbitrary graph, as well as a method of recognizing subgraph isomorphisms. Combined, these results provide a solution to the problem of candidate subcircuit enumeration. These techniques provide both theoretical and practical contributions within design automation and graph theory.

An application of formal analysis to software in a fault-tolerant environment

The paper describes work that represents the culmination of a comprehensive hardware/software modeling and analysis project concerning the Charles Stark Draper Laboratory Fault-Tolerant Processor (FTP). The FTP performs a safety related function at the Integral Fast Reactor (IFR, previously known as the Experimental Breeder Reactor-II) operated by Argonne National Laboratory for the Department of Energy. Previously, we demonstrated the tolerance to hardware failures of data exchange instructions on the FTP (G.H. Chisholm et al., 1987; A.J. Kljaich et al., 1989; A.S. Wojcik et al., 1984; A.S. Wojcik, 1983). We describe a methodology for assuring that the software executing on the FTP is also tolerant to hardware failures. This methodology is based on an abstraction of the program data and control flows in terms of the specification of an abstract application program that operates on the FTP. We then prove the fault tolerance of the abstract application program to hardware and sensor failures. Based on a more detailed specification and analysis of the code that is used in the application software, we demonstrate that this code satisfies the sufficient conditions developed for the abstract application program to claim system fault tolerance.

Design recovery for incomplete combinational logic

Motivated by the problem of reengineering legacy digital circuits for which design information is missing or incomplete, this paper presents a new technique for representing the relationships among the internal components of a combinational circuit. This technique proves to be a powerful tool for redesign, capable of representing internal Boolean relationships in a fully or partially specified multiple-output combinational circuit with a single data structure.

Identification of functional components in combinational circuits

Identifying the subcircuits in a detailed circuit description is a fundamental operation in both circuit validation and design recovery. Existing identification techniques rely on finding an exact match for a subcircuit structure within the description. These techniques fail to identify subcircuits that are functionally equivalent but have been obfuscated because a different technology is being used or because the design has been optimized. This report presents a mechanism for identifying subcircuits that are functionally equivalent, irrespective of obfuscating details. It also describes the initial progress made in transforming detailed circuit descriptions into corresponding descriptions based on subcircuits. Such progress depends on enumerating all of the candidate subcircuits within the original detailed description and functionally matching each candidate. The report presents unique solutions for reducing the amount of computation needed for this enumeration.