Anthony Vacca

Increasing reticle inspection efficiency and reducing wafer printchecks at 14nm using automated defect classification and simulation

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any persons judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the results of both AIMS optical simulation and to actual wafer prints.

Model-based mask verification

One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model. The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing has become ever more complex throughout the years so properly modeling this portion of the process has the potential to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we will show results of a new approach that incorporates mask process modeling. We will also show results of testing a new dynamic mask bias application used during OPC verification.

Comprehensive defect detection featuring die-to-database reflected light inspection

With ever shrinking k1 lithography, overall reticle quality is paramount to ensure high quality image transfer. State-of-the-art reticle inspection systems play two vital roles in reticle manufacturing: quality assurance and manufacturing process feedback. For quality assurance, the system must be capable of detecting all defects of interest to the end user - defects that repeatedly print on wafer, and also those that may reduce the lithography process window. For process monitoring and improvement, the system must be capable of detecting defects at or near the manufacturing limits of mask manufacturing. In order to meet both needs, an inspection system must detect all defect types including pattern errors and contaminates on all mask surfaces including chrome, quartz, and shifter materials. A new advanced inspection method compares both transmitted and reflected light images to the design database. This comprehensive inspection method detects numerous defects that would be missed in a transmitted or reflected only inspection tool. In this study we have tested a new method for detecting reticle defects. Inspection results will be shown from a programmed defect test vehicle as well as a production reticle.

Dry etch yield enhancement by use of after-develop inspection

Decreasing feature sizes combined with high mask error enhancement factors (MEEF) are rapidly causing tighter defect and CD uniformity specifications on photomasks. In general, dry etching photomasks improves feature fidelity but also tends to increase defectivity. Since the first automated mask defect inspection usually occurs after chrome etch, it is difficult to determine if a defect originated with the photoblank or during one of the mask patterning steps (write, develop, and etch). To understand and optimize the dry etch process, After Develop Inspection (ADI) has been developed to isolate the cause of photomask defects. In this study, ADI was used to inspect Cr photomasks incorporating iP3600 and ZEP7000 resists at several thicknesses. The detected defects were analyzed and compared to defects found after etch. A test mask with programmed defects was also created and tested to characterize the sensitivity of this new capability.

Improved reticle requalification accuracy and efficiency via simulation-powered automated defect classification

Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.

Chromeless phase lithography reticle defect inspection challenges and solutions

CPLTM Technology is a promising resolution enhancement technique (RET) to increase the lithography process window at small feature line widths. Successful introduction of a reticle based RET needs to address several reticle manufacturing areas. One key area is reticle inspection. A CPL reticle inspection study has been completed and a best known methodology (BKM) devised. Use of currently available inspection tools and options provides a robust solution for die-to-die inspection. Die-to-database inspection challenges and solutions for optically completed CPL reticles are discussed. Core to the devised BKM is the concept of in-process inspections where the highest sensitivity inspection may not necessarily be performed after the last manufacturing step. The rationale for this BKM is explained in terms of actual manufacturing process flow and most likely defect sources. This rationale also has implications for programmed defect test mask designs in that the choice of defect types need to be linked to a plausible source in the manufacturing process. Often, the choice of a programmed defect type ignores the fact that a naturally occurring defects origin is early in the manufacturing process and would be detected and either repaired or the reticle rejected before subsequent manufacturing steps. Therefore, certain programmed defect types may not be representative of what should be expected on a production mask. Examples such defects are discussed.

A new methodology to specify via and contact layer reticles for maximizing process latitude

It is well known that shrinking k1 factors are making via and contact layers more difficult to print with acceptable latitude and low defectivity. A typical method for improving the common process window is to use embedded attenuated phase shifting masks (EAPSM). However, even with the improved resolution offered by this technology, small deviations in reticle contact size are producing increasingly severe patterning problems - at the extreme, missing contacts. In this study, we conducted an investigation of a production reticle causing repeating wafer defects that passed the reticle manufacturer’s outgoing inspection. We have examined this reticle using a new inspection algorithm that measures reticle contact energy. This technique successfully detected slightly undersized contacts directly corresponding to the coordinates of the repeating wafer defects. However, the reticle contact energy inspection also detected numerous undersized contacts that were not detected by wafer SEM inspection. We have produced and printed to wafer a test reticle with programmed over and under sized contacts in order to create a new reticle specification to detect defective contacts before they are shipped to the wafer fab.

Improved method for measuring and assessing reticle pinhole defects for the 100-nm lithography node

With the approach of the 100nm-lithography node, an accurate and reliable method of measuring reticle pinhole defects becomes necessary to assess the capabilities of high-end reticle inspection equipment. The current measurement method of programmed defect pinholes consists of using a SEM. While this method is repeatable, it does not reliably represent the true nature of a pinhole. Earlier studies have suggested that since the SEM images only a top down view of the pinhole, the measurement does not accurately account for edge wall angle and partial filling which both reduce pinhole transmission and subsequent printability. Since wafer lithography and reticle inspection tools use transmitted illumination, pinhole detection performance based on SEM measurements is often erroneous. In this study, a pinhole test reticle was manufactured to further characterize the capabilities of a transmission method to measure pinholes.

Improved method for measuring and assessing reticle pinhole defects

With the increased resolution of todays lithography processes, reticle pinhole defects are much more printable. Measuring the size of small pinholes using the current SEM method often produces erroneous results when compared to pinhole energy transmission. This is mainly due to the fact that SEMs do not accurately account for edge wall angle and partial filling which can dramatically reduce the pinhole transmission and subsequent printability. Since reticle inspection tools, like wafer steppers and scanners, use transmitted illumination, pinhole detection performance based upon top surface SEM defect sizing is often erroneous for small pinhole diameters. This study first uses simulation to predict printability. Then, a pinhole test reticle is developed with a variety of sub-200nm pinholes. The reticle pinholes are measured with an improved method incorporating transmission and imaged to wafer in order to assess printability.

ArF (193-nm) alternating aperture PSM quartz defect repair and printability for 100-nm node

Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.