Anthony Y. Wong

A high density BiCMOS direct drive array

A BiCMOS (bipolar complementary metal-oxide semiconductor) gate array with nearly the same density as a standard CMOS array has been realized using an advanced 1.5- mu m BiCMOS process and a channelless architecture. A two-input BiCMOS NAND gate has a delay of 800 ps when driving a load of sixteen, which is half the delay in CMOS. Arrays with up to 123 K equivalent gates can be achieved with an optimal ratio of CMOS logic gates and BiCMOS blocks.<<ETX>>

A sub half-ns 237 K gate CMOS compacted array

A family of third-generation compacted arrays with up to 237 K gates has been developed using a channelless architecture. 1- mu m HCMOS (high-speed complementary metal-oxide semiconductor) technology with 0.75- mu m effective channel length was used to fabricate the device. Complex designs with up to 100 K utilized gates can be implemented on a single chip using this technology. Switching performance of 400 ps is achieved on two input NAND gates with typical loading.<<ETX>>