Anton deVilliers

Manufacturability considerations for DSA

Implementation of Directed Self-Assembly (DSA) as a viable lithographic technology for high volume manufacturing will require significant efforts to co-optimize the DSA process options and constraints with existing work flows. These work flows include established etch stacks, integration schemes, and design layout principles. The two foremost patterning schemes for DSA, chemoepitaxy and graphoepitaxy, each have their own advantages and disadvantages. Chemoepitaxy is well suited for regular repeating patterns, but has challenges when non-periodic design elements are required. As the line-space polystyrene-block-polymethylmethacrylate chemoepitaxy DSA processes mature, considerable progress has been made on reducing the density of topological (dislocation and disclination) defects but little is known about the existence of 3D buried defects and their subsequent pattern transfer to underlayers. In this paper, we highlight the emergence of a specific type of buried bridging defect within our two 28 nm pitch DSA flows and summarize our efforts to characterize and eliminate the buried defects using process, materials, and plasma-etch optimization. We also discuss how the optimization and removal of the buried defects impacts both the process window and pitch multiplication, facilitates measurement of the pattern roughness rectification, and demonstrate hard-mask open within a back-end-of-line integration flow. Finally, since graphoepitaxy has intrinsic benefits in terms of design flexibility when compared to chemoepitaxy, we highlight our initial investigations on implementing high-chi block copolymer patterning using multiple graphoepitaxy flows to realize sub-20 nm pitch line-space patterns and discuss the benefits of using high-chi block copolymers for roughness reduction.

Simulation-based pattern matching using scanner metrology and design data to reduce reliance on CD metrology

Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use of scanner metrology and design data and minimizes the reliance on wafer CD metrology. A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe to two other recipes that were obtained from the new, optical model based matching method. In the following sections, we describe the implementation of both methods, provide their predicted and actual improvements after matching, and compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations on the relative merits of each method for a variety of use cases.

Resist freezing process challenges of cross pattern applications

Three resist freezing methods (fluoride plasma, chemical and thermal freezing) were studied for double patterning cross pattern by printing the second layer directly on top of the first resist layer. Different methods show different challenges: plasma freezing is very hard to remove footing on both layers; Chemical freezing first layer CD will grow after completion of second pattern; thermal freezing will change line curvature when the CD is smaller than 50nm, if first layer is wave type pattern.

Wafer quality analysis of various scribe line mark designs

Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment. Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are changed as the wafers go through various processes and are buried underneath complex film stacks. These processes and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on SLMs and experimentally verifies results using various structures.

Improving aberration control with application specific optimization using computational lithography

As the industry drives to lower k1 imaging we commonly accept the use of higher NA imaging and advanced illumination conditions. The advent of this technology shift has given rise to very exotic pupil spread functions that have some areas of high thermal energy density creating new modeling and control challenges. Modern scanners are equipped with advanced lens manipulators that introduce controlled adjustments of the lens elements to counteract the lens aberrations existing in the system. However, there are some specific non-correctable aberration modes that are detrimental to important structures. In this paper, we introduce a methodology for minimizing the impact of aberrations for specific designs at hand. We employ computational lithography to analyze the design being imaged, and then devise a lens manipulator control scheme aimed at optimizing the aberration level for the specific design. The optimization scheme does not minimize the overall aberration, but directs the aberration control to optimize the imaging performance, such as CD control or process window, for the target design. Through computational lithography, we can identify the aberration modes that are most detrimental to the design, and also correlations between imaging responses of independent aberration modes. Then an optimization algorithm is applied to determine how to use the lens manipulators to drive the aberrations modes to levels that are best for the specified imaging performance metric achievable with the tool. We show an example where this method is applied to an aggressive memory device imaged with an advanced ArF scanner. We demonstrate with both simulation and experimental data that this application specific tool optimization successfully compensated for the thermal induced aberrations dynamically, improving the imaging performance consistently through the lot.

LER improvement for sub-32nm pitch self-aligned quadruple patterning (SAQP) at back end of line (BEOL)

Critical back end of line (BEOL) Mx patterning at 7nm technology node and beyond requires sub-36nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the front up approach for Mx grid patterning for most of industry. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed SAQP approach since 10nm node technology, BEOL Mx SAQP is challenging owing to the required usage of significantly lower temperature budgets for film stack deposition. This has an adverse impact on the material properties of the as-deposited films leading to emergence of several challenges for etch including selectivity, uniformity and roughness. In this presentation we will highlight those unique etch challenges associated with our BEOL Mx SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7nm BEOL Mx, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32nm pitch BEOL SAQP pattern.

Anti-spacer double patterning

With extreme UV not ready for HVM for the 20nm and 14nm nodes, double patterning options that extend the use of 193nm immersion lithography beyond the optical resolution limits, such as LELE (Litho-Etch-Litho-Etch) and SADP (Self Aligned Double Patterning), are being used for critical layers for these nodes. LELE requires very stringent overlay capability of the optical exposure tool. The spacer scheme of SADP starts with a conformal film of material around the mandrels and etched along the mandrel sidewalls to form patterns with doubled frequency. SADP, while having the advantage of being a self-aligned process, adds a number of process steps and strict control of the mandrel profile is required. In this paper, we will demonstrate a novel technique - ASDP (Anti-Spacer Double Patterning), which uses only spin-on materials to achieve self-aligned double patterning. After initial resist patterning, an Anti-Spacer Generator (ASG) material is coated on the resist pattern to create the developable spacer region. Another layer of material is then coated and processed to generate the second pattern in between the first resist pattern. We were able to define 37.5nm half pitch pattern features using this technique as well as sub-resolution features for an asymmetric pattern. In this paper we will review the capability of the process in terms of CD control and LWR (line width roughness) and discuss the limitations of the process.

High speed EUV using post processing and self-aligned double patterning as a speed enhancement technique

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Process transfer strategies between ASML immersion scanners

A top challenge for Photolithographers during a process transfer involving multiple-generation scanners is tool matching. In a more general sense, the task is to ensure that the wafer printing results in the receiving fab will match or even exceed those of the originating fab. In this paper we report on two strategies that we developed to perform a photo process transfer that is tailored to the scanners capabilities. The first strategy presented describes a method to match the CD performance of the product features on the transferred scanner. A second strategy is then presented which considers also the down-stream process tools and seeks to optimize the process for yield. Results presented include: ASML TWINSCANTM XT:1700i and XT:1900i scanners 1D printing results from a line-space test reticle, parametric sensitivity calculations for the two scanners on 1D patterns, simulation predictions for a process-optimized scanner-matching procedure, and final wafer results on 2D production patterns. Effectiveness of the optimization strategies was then concluded.

Multi-color fly-cut-SAQP for reduced process variation

Multi-patterning processes such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) present new challenges to the semiconductor device manufacturing such as increased relative cost to previous nodes, longer cycle times, and increased (local) edge placement error between grid and cut/block layers. As the scaling requirements continue, the factors driving both EPE and electrical yield such as overlay, critical dimension control (CDU) and stochastics (LCDU) become greater concerns to multi-patterning. In addition to lithographic process variations, the unit processes such as plasma/vapor etch, deposition, wet/cleans can contributes additional variation in spacer/mandrel profiles leading to poor CDU control and ultimately within-wafer pitch walking. In this paper, we outline alternative SAQP integration schemes to improve the feature profile of both mandrel and spacer to minimize process variability. This patterning scheme designated as fly-cut SAQP introduces new concepts such top spacer removal by chemical-mechanical planarization, mandrel foot mitigation layers, multi-layered mandrel for accurate polish end-point and void-free gap fill to realize high fidelity transfer to the underlying hardmask. Finally, we will demonstrate the effectiveness for this new integration scheme as a candidate for multi-color/self-aligned block (SAB) and highlight the additional benefits of using such an approach.