Antonio Carneiro Mesquita

Chromosome representation through adjacency matrix in evolutionary circuits synthesis

The use of adjacency matrices to the chromosome coding in evolutionary circuits techniques is proposed. The approach is shown to overcome some of the drawbacks associated with other coding schemes simplifying the implementation of the evolution process. It is particularly shown that the proposed coding scheme reduces considerably the generation of anomalous circuits increasing the efficiency of the overall process. Other important issues such as fault tolerance, sensitivity and robustness of the synthesized circuits are addressed.

Evolutionary synthesis of analog circuits using only MOS transistors

The synthesis of analog circuits assuming a hypothetical intrinsic evolutionary integrated hardware platform containing only CMOS transistors is examined. It is shown that to efficiently synthesize analog circuits both topology and transistors sizing should be treated separately. To this end a flexible chromosome coding scheme able to generate the most common analog building blocks and the inclusion in the genetic algorithm of a separate transistor sizing step are proposed.

An experiment on nonlinear synthesis using evolutionary techniques based only on CMOS transistors

An experiment to perform analog circuits synthesis, using evolutionary techniques applied to circuits containing only integrated MOS transistors, is discussed. MOS transistors can operate as capacitors, resistors, switches and bipolar transistors. In an intrinsic evolutionary context, this simplifies considerably the design of field programmable analog arrays. The limitations of the approach are discussed in the paper.

Optimized datapath design by evolutionary computation

High-level design entry tools offer a nice framework to deal with todays complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.

ATPG for fault diagnosis on analog electrical networks using evolutionary techniques

This paper proposes a method for automated test pattern generation for fault diagnosis on continuous-time analog electrical networks based on evolutionary techniques. The paper states a method for coding a generic algorithm, based on a given heuristic, that are able to generate a set of optimum frequencies capable of disclosing parametric faults. The method itself is generic, and not based on specific or ad hoc features at all.

Extraction of static parameters to extend the EKV model to cryogenic temperatures

The electric simulation models of CMOS devices provided by the foundries are valid at the standard temperature range of -55 to 125°C. These models are not suitable to the design of circuits intended to operate at cryogenic temperatures as is the case of cooled infrared readout circuits. To generate a library of CMOS electric simulation models valid at cryogenic temperatures, the characterization of wide and long CMOS transistors are investigated. The EKV2.6 model, which is an industry-standard compact simulation model for CMOS transistors, is used in this characterization. Due to its relatively small number of parameters the EKV2.6 model is well suited to the parameter extraction procedures when not disposing of an expensive automated parameter extraction system. It is shown that to provide an appropriate IV-characteristic fit to cryogenic temperature range it is sufficient to extract only five parameters - threshold voltage VT0, body effect GAMMA, Fermi potential PHI, transconductance factor KP, and the vertical characteristic field for mobility reduction E0. The proposed approach is tested in a standard 0.35μm/3.3V CMOS technology, employing extraction procedures recommended in the literature. Simulations are made with a BSIM3V3 standard library provided by the foundry changing the temperature parameter and with the generated library. The results are compared with the measurements. As expected, the simulations made with the generated library show a best agreement with the performed measurements at 77K than the simulations with the BSIM3V3 model. The proposed methodology is shown to be particularly effective above strong freeze-out temperature.

Evolutionary synthesis of low-sensitivity equalizers using adjacency matrix representation

An evolutionary synthesis method to design low-sensitivity IIR filters with linear phase in the passband is presented. The method uses a chromosome coding scheme based on the graph adjacency matrix. It is shown that the proposed chromosome representation enables to easily verify invalid individuals during the evolutionary process. The efficiency of the proposed algorithm is tested in the synthesis of a fourth-order linear phase elliptic lowpass digital filter.

Using genetic programming and high level synthesis to design optimized datapath

This paper presents a methodology to design optimized electronic digital systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-level synthesis tools to automatically improve design structural quality (area measure). A two-stage, multiobjective optimization algorithm is used to search for circuits with the desired functionality subjected additionally to chip area constraints. Experiment with a square-root approximation datapath design targeted to FPGA exemplifies the proposed methodology.

Evolutionary synthesis of low-sensitivity antenna matching networks using adjacency matrix representation

An evolutionary synthesis method to generate impedance matching networks with low sensitivity is presented. The method uses a chromosome coding scheme based on the adjacency matrix to represent the impedance networks. It is shown that the performance of the evolutionary algorithm in this particular synthesis may be considerably improved by including an optimization step to tune the component values of the impedance network. The efficiency of the proposed algorithm is tested in the synthesis of an impedance network for a monopole whip antenna and the results are compared with other examples found in the literature.

Automatic synthesis of lossless matching networks

An evolutionary method for the synthesis of impedance matching networks is proposed. The algorithm uses a coding scheme based on the graph adjacency matrix to represent the topology and component values of the circuit. In order to generate realistic solutions the sensitivities of the network parameters are accounted for during the synthesis process. To this end a closed form expression for the Transducer Power Gain sensitivity with respect to the component values of LC lossless matching networks is derived, in such a way that the effects of the components tolerance on the matching network performance can easily be quantified. The evolutionary algorithm efficiency is tested in the synthesis of an impedance matching network and the results are compared with other methods found in the literature.