Antonio Gentile

A Sliced Coprocessor for Native Clifford Algebra Operations

Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocessor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. S-CliffoSor is a sliced coprocessor that can be replicated for parallel execution of concurrent Clifford operations. A single slice has been designed, implemented and tested on the Celoxica Inc. RC1000 board. The experimental results show the potential to achieve a 3times speedup for Clifford sums and 4times speedup for Clifford products compared to against the analogous operations in the software library generator GAIGEN.

Focal-plane processing architectures for real-time hyperspectral image processing

Real-time image processing requires high computational and I/O throughputs obtained by use of optoelectronic system solutions. A novel architecture that uses focal-plane optoelectronic-area I/O with a fine-grain, low-memory, single-instruction-multiple-data (SIMD) processor array is presented as an efficient computational solution for real-time hyperspectral image processing. The architecture is evaluated by use of realistic workloads to determine data throughputs, processing demands, and storage requirements. We show that traditional store-and-process system performance is inadequate for this application domain, whereas the focal-plane SIMD architecture is capable of supporting real-time performances with sustained operation throughputs of 500-1500 gigaoperations/s. The focal-plane architecture exploits the direct coupling between sensor and parallel-processor arrays to alleviate data-bandwidth requirements, allowing computation to be performed in a stream-parallel computation model, while data arrive from the sensors.

Real-Time Image Processing on a Focal Plane SIMD Array

Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limitations (size, weight, and power). The SIMD Pixel Processor (SIMPil) has been designed at Georgia Tech to address these problems. In SIMPil, an image sensor array (focal plane) is integrated on top of a SIMD computing layer, where processing elements (PEs) are connected in a torus. A prototype processing element has been implemented in 0.8 μm CMOS technology. This paper evaluates the effectiveness of the SIMPil design on a set of important image applications. A target SIMPil system is described, which is capable of operating in the Tops/sec range in Gigascale technology. Simulation results indicate sustained operation throughput in the range of 100–1000 Gops/sec. These results support the design choices and suggest that more complex, multistage applications can be implemented to execute at real-time frame rates.

Real-time vector quantization-based image compression on the SIMPil low memory SIMD architecture

Vector quantization (VQ) has become a popular technique for image compression. While conventional unstructured VQs have the potential of achieving the best theoretical performance, they are also demanding in storage and computational requirements. A significant amount of current research on VQ implementations addresses increasing the speed of image encoding, which is one of the most computationally expensive operations. This is typically accomplished by imposing structures, exploiting properties of the distance measure, or developing efficient and fast implementations. This paper proposes a parallel implementation of a full-search VQ encoding algorithm using a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor (SIMPil) being developed at Georgia Tech. This implementation fully exposes the available parallelism of the encoding process and exploits the processing and I/O capabilities of the processor, resulting in a system that can perform real-time image and video compression. The proposed implementation encodes a large region of the original image at once, replacing each constituent input block with its corresponding VQ codeword index. Preliminary simulation results indicate that the proposed implementation is capable of sustain real-time frame rates. A prototype single node SIMPil implementation has been fabricated by MOSIS in 0.8 /spl mu/m CMOS, and is being evaluated.

CliffoSor: a parallel embedded architecture for geometric algebra and computer graphics

Geometric object representation and their transformations are the two key aspects in computer graphics applications. Traditionally, compute-intensive matrix calculations are involved to model and render 3D scenery. Geometric algebra (a.k.a. Clifford algebra) is gaining growing attention for its natural way to model geometric facts coupled with its being a powerful analytical tool for symbolic calculations. In this paper, the architecture of CliffoSor (Clifford Processor) is introduced. ClifforSor is an embedded parallel coprocessing core that offers direct hardware support to Clifford algebra operators. A prototype implementation on an FPGA board is detailed. Initial test results show more than 4/spl times/ speedup for Clifford products against the analogous operations in GAIGEN, a standard geometric algebra library generator for general purpose processors.

The impact of grain size on the efficiency of embedded SIMD image processing architectures

Pixel-per-processing element (PPE) ratio-the amount of image data directly mapped to each processing element-has a significant impact on the area and energy efficiency of embedded SIMD architectures for image processing applications. This paper quantitatively evaluates the impact of PPE ratio on system performance and efficiency for focal-plane SIMD image processing architectures by comparing throughput, area efficiency, and energy efficiency for a range of common application kernels using architectural and workload simulation. While the impact of grain size is affected by the mix of executed instructions within an application program, the most efficient PPE ratio often does not occur at PE grain size extremes (i.e., one pixel per processor or one processor per image). In this study, a set of four image processing application tasks is implemented on eight different SIMD configurations. Each configuration has a different PPE ratio and a different amount of local memory. Cycle accurate simulation and analytical technology modeling allows assessment of execution performance, area efficiency, and energy efficiency for each configuration. Results show the highest area and energy efficiency are achieved at PPE ratios between 16 and 256. Using these evaluation techniques (application grain size retargeting combined with area and energy technology modeling), a new class of efficient, embedded SIMD architectures for image processing can be designed.

Continuous Hand Openness Detection Using a Kinect-Like Device

This paper presents a novel method to reproduce in real time the opening and closing gestures of a human hand, animating a three-dimensional model of it. In other works, this result can be achieved by mapping a set of significant points of a real hand on the corresponding points of the model to animate. We propose an alternative way to produce the same effect without mapping points, but using a level-based estimation of the degree of opening of the hand. The experiments have been executed using Microsoft KinectTM, but the method would work on any other Kinect-like devices (as defined herein). The results obtained are particularly encouraging and demonstrate real-time performance of the system.

Impact of power density limitation in gigascale integration for the SIMD pixel processor

Gigascale Integration (GSI) enables a new generation of monolithic focal plane processing systems built with billion-transistor chips. As this technology matures, fundamental technology limitations on wire interconnects and power dissipation will become the performance bottleneck. This paper presents system performance projections for GSI technologies under these constraints. Architectural models and workload characterization are integrated to identify viable future system implementations. The SIMD Pixel processor (SIMPil) is selected as the architecture for evaluation, and an image processing application suite is programmed to characterize the workload. Projections for SIMPil systems show that over three orders of magnitude improvement is achievable by 2012 in both system throughput and image resolution. System power consumption is contained below 50 W for a 52,900 processor system in 50 nm technology. The SIMPil architecture design space is explored, and opportunities for more aggressive designs within power density limits are examined.

Real-Time Hand Pose Recognition Based on a Neural Network Using Microsoft Kinect

The Microsoft Kinect sensor is largely used to detect and recognize body gestures and layout with enough reliability, accuracy and precision in a quite simple way. However, the pretty low resolution of the optical sensors does not allow the device to detect gestures of body parts, such as the fingers of a hand, with the same straightforwardness. Given the clear application of this technology to the field of the user interaction within immersive multimedia environments, there is the actual need to have a reliable and effective method to detect the pose of some body parts. In this paper we propose a method based on a neural network to detect in real time the hand pose, to recognize whether it is closed or not. The neural network is used to process information of color, depth and skeleton coming from the Kinect device. This information is preprocessed to extract some significant feature. The output of the neural network is then filtered with a time average, to reduce the noise due to the fluctuation of the input data. We analyze and discuss three possible implementations of the proposed method, obtaining an accuracy of 90% under good conditions of lighting and background, and even reaching the 95% in best cases, in real time.

Exploitation of Mobile Access to Context-Based Information in Cultural Heritage Fruition

More than one billion smartphone users are estimated by 2014. With this in mind, visiting cultural heritage sites and exhibits may offer new level of engagement and entertainment just reaching down in our pockets. With orders of magnitude more computational horsepower than a five years-old desktop machine, stuffed with all sorts of sensors, these modern gizmos have a largely untapped potential to gain us access to personalized and on-demand information wherever it is needed. This paper is exactly about this, exploring with several case studies how these devices may become part of a memorable experience during a visit that one may want to share with friends and relatives. Specifically, the paper will focus on the definition of the user-experience (UX), on integration issues, and on context detection within augmented environments in cultural heritage sites, along with a discussion on the lessons learnt.