António J.N. Batista

ATCA/xTCA-based hardware for control and data acquisition on Nuclear Fusion fast control plant systems

In contemporary control and data acquisition systems for Nuclear Fusion devices, the galloping need for high channel density and real-time multi-input-multi-output (MIMO) support gave rise to a new generation of hardware architecture based on the Advanced Telecommunications Computing Architecture (ATCA) specification. In addition, ATCA successfully delivered solutions in other sensitive issues such as form-factor component area, power dissipation and redundancy, complying with the high complexity and security required for such systems. Experience has showed, however, that due to its aforementioned complexity, such hardware devices can yield to a lengthy development. Furthermore, the ATCA specification is, as yet, somewhat undefined for instrumentation applications, more so within the specificities of Plasma Physics applied devices. The entitled “xTCA” specification is currently being developed for those purposes. Based on the ATCA itself, it will define new functionalities that standardize and facilitate hardware development for device operation in a Fusion control plant environment - most notably, dedicated timing and input-output (IO) port assignment on the Rear Transition Module (RTM). The prototype hereby presented is an xTCA Peripheral Component Interface (PCIe) switch Advanced Mezzanine Card (AMC) carrier blade. The device serves as a hub, as to control and handle I/O data from its parent nodes existing within the same xTCA shelf through its proprietary fabric channels in dual-star topology. Parent node blades, under development, are equally linked through xTCAs agnostic fabric in full-mesh topology, as to attain system MIMO functionality from all I/O endpoints. The switch blade carries up to four AMC modules, adding up to modularity and versatility. This allows for a much more independent and speedier hardware development, as dedicated AMC modules, such as data processing and storage devices, can be simultaneously projected. Commercial off-the-shelf (COTS) AMC products are readily available and may also be immediately integrated in the system.

A distributed system for fast timing and event management on the mast experiment

This paper describes an expandable and distributed system that produces the timing signals for the correct operation of the MAST diagnostic and data acquisition systems and performs the broadcast, processing and recording of the occurrence time of externally generated events for real-time control purposes. The hardware will be implemented using the VME and CAMAC standards. The software control interface will be incorporated in the MAST control and data acquisition system, allowing for an easy database access of the system timing parameters.

ATCA fast data acquisition and processing system for JET gamma-ray cameras upgrade diagnostic

Nuclear reaction gamma-ray diagnosis is one of the important techniques used for studying confined fast-ions. The Joint European Torus (JET) gamma-ray camera diagnostic provides information on the spatial distribution of fast ions. The system is currently being upgraded and should allow gamma-ray image measurements in high power deuterium JET pulses, and eventually in deuterium-tritium discharges. In order to fully exploit the diagnostic capabilities it is mandatory to develop a reliable, maintainable, multi-channel spectroscopy data acquisition and real-time processing (DAQP) system, which shares much of the common development for other specific implementation like Gamma-ray spectroscopy. The DAQP system is based on the Advanced Telecommunications Computing Architecture (ATCA) and contains a 6 GFLOPS x86-based control unit and three transient recorder and processing (TRP) modules, to cope with the two arrays of collimators (10 horizontal + 9 vertical lines of sight), interconnected through PCI Express (PCIe) links. Each TRP module features 8 channels of 13 bit resolution sampling at 250 MHz, 4GByte of local memory and two field programmable gate arrays able to perform complex trigger managing modes and allowing real time analyses (pulse height analyzer and pile-up discrimination), minimizing data storage and transfer issues. The DAQP system aims at overcoming the problem of storing large amount of data during long discharges. A raw/processed mode is being developed where the acquired raw data follows two parallel paths: besides being directly stored in the on-board memory, it is processed and streamed in real-time through PCIe links. This procedure is expected to greatly reduce the amount of data and possible allow continuous operation of the diagnostic. During commissioning and when data validation is required, the 4 GB raw data will be executed on the x86 control unit through a well known algorithm and the result cross checked with the processed data.

A distributed real-time system for event-driven control and dynamic data acquisition on a fusion plasma experiment

A distributed real-time trigger and timing system, designed in a tree-type topology and implemented in VME and CAMAC versions, has been developed for a magnetic confinement fusion experiment. It provides sub-microsecond time latencies for the transport of small data objects allowing event-driven discharge control with failure counteraction, dynamic pre-trigger sampling and event recording as well as accurate simultaneous triggers and synchronism on all nodes with acceptable optimality and predictability of timeliness. This paper describes the technical characteristics of the hardware components (central unit composed by one or more reflector crates, event and synchronism reflector cards, event and pulse node module, fan-out and fan-in modules) as well as software for both tests and integration on a global data acquisition system. The results of laboratory operation for several configurations and the overall performance of the system are presented and analysed.

HDL based FPGA interface library for data acquisition and multipurpose real time algorithm processing

The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, as the management of internal hardware clocks, that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s. The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few MHz). A brief description of this modular code is presented and examples of its use as interface with end user algorithms, including a PHA with PUR, are described.

Intelligent Platform Management Controller for nuclear fusion fast plant system controllers

An Intelligent Platform Management Controller (IPMC) is being developed by IPFN/IST. This controller will be integrated in the Advanced Telecommunications Computing Architecture (ATCA) and Advanced Mezzanine Cards (AMC) modules that are under development for application in nuclear fusion experiments such as the ITER Fast Plant System Controller (FPSC) prototype. This controller in addition with the Shelf Manager module is responsible for the management of hardware failure, redundancy procedures, and hot swapping of the modules in the ATCA crate. The verification of compatibility between modules that share ATCA resources, the power management of each module, temperature monitoring, and fan control are, as well, tasks that the IPMC has the responsibility to manage. Other important functions of the controller are the programming of ATCA and AMC modules firmware, application specific program selection, and firmware version control. In this paper, the hardware architecture of the IPMC implementation at IPFN ATCA modules will be described.

An overview of the ATCA ® timing and synchronization resources for Control and Data Acquisition

Instruments for Control and Data Acquisition (CDAQ) require a pervasive embedded network able to provide accurate timing and synchronization signals to all digitalization/reconstruction devices and control processes of a CDAQ system.

ITER prototype fast plant system controller based on ATCA platform

The ITER Fast Plant System Controllers (FPSC) are based on embedded technologies and will be devoted to both data acquisition tasks (sampling rates >1 kSPS) and control purposes in closed-control loops whose cycle times are below 1 ms. Fast Controllers will be dedicated industrial controllers with the ability to: i) supervise other fast and/or slow controllers; ii) interface to actuators and sensors and high performance networks. This contribution presents an FPSC prototype, specialized for data acquisition, based on the ATCA (Advanced Telecommunications Computing Architecture) standard. This prototyping activity contributes to the ITER Plant Control Design Handbook (PCDH) effort of standardization, specifically regarding fast controller characteristics. For the prototype, IPFN is developing a new family of ATCA modules targeting ITER requirements. The modules comprise an AMC carrier/data hub/timing hub compliant with the upcoming ATCA extensions for Physics and a multi-channel with galvanic isolation hot-swappable digitizer designed for serviceability. The design and test of a peer-to-peer communications layer for the implementation of a reflective memory over PCI Express and the design and test of an IEEE-1588 transport layer over a high performance serial link was also performed. In this work, a complete description of the solution is presented as well as the integration of the controller into the standard CODAC environment. The most relevant results of real tests will be addressed, focusing in the benefits and limitations of the applied technologies.

The control and data acquisition system for the ISTTOK heavy ion beam diagnostic

A heavy ion beam diagnostic for the tokamak ISTTOK has been developed with the aim of measuring the temporal evolution of the electron density, plasma potential, electron temperature and poloidal magnetic field radial profiles. The control and data acquisition system for this diagnostic is described. This system was designed in a modular and versatile approach based on locally developed VME timing, waveform generator and digitizer modules. Its integration into the ISTTOK control and data acquisition system as well as the first experimental results are also reported.

Test results of an ITER relevant FPGA when irradiated with neutrons

The data acquisition and control instrumentation in port cell cubicles of tokamak ITER will be irradiated with neutrons, during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I&C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories.