Antonio Liscidini

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.

A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications

Employing feedback circuits in RF front-ends can be a key aspect for easy reconfiguration of multistandard receivers. A narrow-band filter can shape the frequency transfer function and, by reflection due to the feedback network, the input impedance. Switching one single filter component thus allows selecting a different standard. We introduce a voltage-voltage feedback low noise amplifier that, besides being easily reconfigurable, shows roughly the same noise and better linearity, for same power consumption, as the conventional inductively degenerated topology. A direct conversion front-end, including the LNA and I and Q mixers, tailored to WLAN applications in the 5-6 GHz range, has been realized in a 0.25-/spl mu/m SiGe BiCMOS process. Prototypes show the following performances: 2.5 dB NF, 31.5 dB gain, -9.5dBm IIP3, and +23dBm minimum IIP2 while consuming 16 mA from a 2.5 V supply.

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90 nm CMOS process and consumes 3 mA from 1.2 V when operating at 25 MHz. The native Vernier resolution of the TDC is 5.8 ps, while the total noise integrated over a bandwidth of 800 kHz yields an equivalent TDC resolution of 3.2 ps.

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V

Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping

A novel class of filters (called pipe filters) that features in-band noise reduction is presented and a current mode biquad cell based on cross-connected cascoded devices is introduced. The presented solution gives in-band high-pass noise shaping and passive pre-filtering of out-of-band blockers. This results in both low in-band noise and high out-of-band IIP3. A 4th-order lowpass prototype in 90 nm CMOS for WCDMA application features 32 μW in-band noise (when integrated over the 2 MHz bandwidth as defined by the standard) and +36 dBm out-of-band IIP3 which results in a 75 dB SFDR with 1.25 mW power consumption. Active die area is 0.5 mm2.

Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications

Two very compact and low power quadrature receivers for ZigBee applications are presented. Area and power savings are obtained through both current reuse and oscillator tank sharing between the I and Q paths. Since this choice can cause I and Q amplitude/phase mismatches, the conversion gain is analyzed and a technique to minimize these errors is implemented. Moreover, since using a single tank makes quadrature generation at the local oscillator level costly and power-hungry, two alternative quadrature generation techniques in the RF path are proposed, together with the corresponding input matching strategies.

SAW-less analog front-end receivers for TDD and FDD

A multistandard SAW-less receiver is designed exploring a current-mode architecture. A class-AB common-gate transformer-based low-noise transconductor amplifier (LNTA) is used to provide high linearity and harmonic filtering. A resonant passive mixer is adopted in order to allow the current-mode operation and improve the harmonic rejection. A low-power divider with intrinsic 25% duty-cycle is introduced to drive the passive mixer. A second-order Rauch biquad with complex poles makes-up the IQ blocker tolerant baseband. The receiver is designed to be suitable for SAW-less TDD and typical FDD applications with 3.8 and 1.9 dB of NF and > 18 and > 16 dBm of IIP3, respectively, using only 32 mW for each receiver.

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning

A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The new tuning circuitry does not appreciably affect the intrinsic oscillator phase noise and allows to trim the frequency with a programmable resolution for calibration and multi-standard operation. A prototype integrated in 65 nm CMOS technology exhibits a phase noise of @ 1 MHz drawing 16 mA from a supply of 1.8 V, resulting in a FoM of 183 dBc/Hz. The active area is 700 450.

Time to digital converter based on a 2-dimensions Vernier architecture

A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7bits TDC prototype realized in 65nm CMOS technology is presented. The chip has a resolution of 4.8ps with a power consumption of 1.7mW at a conversion rate of 50Msps.

Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies

A unified description of multiple feedback common-gate low-noise amplifiers (LNAs) is presented, providing analytical expressions for gain, noise figure, linearity, and stability conditions. Moreover, from the theory, a new methodology for LNA optimization is developed. This new approach, called adaptive optimization, uses the ability to reconfigure the feedback network to match the amplifier characteristics to the changing working conditions. Results of simulation of LNAs with different feedback types are shown, and they confirm the theory presented.