Antonio Montalvo

Toward a general-purpose analog VLSI neural network with on-chip learning

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

An analog VLSI neural network with on-chip perturbation learning

An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, high-volume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K /spl mu/m/sup 2/ in a 2-/spl mu/m technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in tens of milliseconds and 4-b parity in hundreds of milliseconds.