Antonio Rubio

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect. >

Experimental comparison of substrate noise coupling using different wafer types

Measurements of substrate coupled noise in a mixed-signal test IC are presented. This IC was manufactured with different types of wafers, and noise levels measured in heavily-doped epi wafers are about three times larger than those obtained in lightly doped ones. It is determined that, due to package parasitics, noise at the supply lines will easily be the major contributor to substrate-coupled disturbances, both at the digital and at the analog ends. Supply lines interact with the substrate mainly through the substrate contacts of both of the circuit core and the ring of pads. The measurements contribute to establishing a list of priorities in the actions to reduce the noise that reaches the analog section.

Noise generation and coupling mechanisms in deep-submicron ICs

On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms.

Substrate coupling evaluation in BiCMOS technology

The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-/spl mu/m BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring.

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.

An approach to dynamic power consumption current testing of CMOS ICs

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.

An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.

Analysis of crosstalk interference in CMOS integrated circuits

The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated. >

Analysis and modeling of MOS devices with gate oxide short failures

A circuit level model for failures causing shorts in the oxide of the gate electrode (GOS) is presented. Experimental results show that the influence of the width of a short between gate and channel in a MOS device is low in comparison with the location in the length direction. The model takes advantage of this result. A unidimensional (length) model for GOS faults is proposed. The experimental results have been obtained by measuring devices with faults where the failures have been introduced by design. The model reduces the complexity of electrical simulations (in comparison with previous unidimensional models) when parametric deviations on an assumed GOS-faulty circuit are analyzed. Results verifying the adequacy of the models and comparison with other research data are presented, considering the effect of the failure on the input and output characteristics of the devices.<<ETX>>

Challenges for signal integrity prediction in the next decade

Abstract Noise caused by the activity of integrated circuits is a limiting factor for the development of future VLSI circuits. Transients of voltages and currents couple perturbations to the co-integrated circuits where the most effective medium to propagate noise is the silicon substrate. The effect is especially important where high-speed digital circuits are integrated together with highly sensitive analog sections, which is the case of modern communication transceivers. Taking into account the effect of noise during the circuit design requires a fine electrical modeling of the substrate and noise generation. The capability of substrate to propagate signals from DC to very high frequencies has to be understood and modeled, together with the role of doping profile and topology of doped regions (layout). In this tutorial paper the sources, propagation of noise and sensitivity of MOS circuits are presented and its trend in the next technology generations is evaluated. The challenges that modeling techniques and CAD tools have to face are commented, and the key points and more likely solutions are discussed.