Antonis Papanikolaou

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moores law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are capable of providing all existing Pareto configurations achieving optimal energy/delay tradeoffs, and this is applicable for the full range of all possible delay constraints. Based on such techniques, a transistor-level implementation is also presented to allow a discrete set of Pareto configurations (from high-speed to low-energy) to be selected at run-time. This implementation has been validated via SPICE simulations for a 65-nm CMOS technology, confirming that a very wide range in delay (more than a factor 2) and energy consumption (up to 40%) can be achieved at the SRAM level, including process variability impact effects present in CMOS nanometer technologies.

Time and workload dependent device variability in circuit simulations

Simulations of an inverter and a 32-bit SRAM bit slice are performed based on an atomistic approach. The circuits devices are populated with individual defects, which have realistic carrier-capture and emission behaviour. The wide distribution of defect time scales, accounts for both fast (Random Telegraph Noise - RTN) and near-permanent (Bias Temperature Instability - BTI) defects. The atomistic property of the model allows the detection of workload dependency in the delay of both circuits.

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

Physical design implementation of segmented buses to reduce communication energy

The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, segmented buses have gained interest in the architectural community. However, the netlist topology and the physical design stage significantly influence the final communication energy cost. We present in this paper an automated way to implement a netlist consisting of hard macro blocks, which are interconnected with heavily segmented buses in an energy optimal fashion for communication. We optimize the network wires energy dissipation in two separate, but related steps: minimizing the number of segments for active communication paths at the first step (block ordering), followed by the activity aware floorplanning step to minimize the physical length of these segments. Energy gains of up to a factor of 4 are achieved compared to a standard system implementation using a shared bus. Especially, the block ordering step contributes significantly to the network energy optimization process.

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

This paper presents a methodology which can substantially reduce the bus power consumption in memory dominated systems. It systematically combines an activity driven placement of the memories and a bus segmentation approach for the interconnect to localize the wire switching activity and minimize the associated wire capacitive load of the memory bus. A factor of 2.8 in bus power reduction is achieved for a real life design while maintaining the same performance.

Global interconnect trade-off for technology over memory modules to application level: case study

In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.

Propagating variability from technology to system level

As CMOS technology feature sizes decrease, variability more and more jeopardizes system level parametric and functional yield. This paper proposes a framework that can capture variability at all levels in the design flow. It offers a correlated view on yield, timing, dynamic and static energy. Preservation on rare events in variability distributions is obtained by the Weighted Monte Carlo technique.

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area, and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.

System-level process variability compensation on memory organizations of dynamic applications: a case study

Process variability and the dynamism of new applications have a tremendous impact on both the performance and the energy consumption of memory organizations of embedded systems. In this paper, we explore the combination of code transformations at compilation time and architectural-level techniques to tackle both problems, introducing a new methodology to combine them in an integrated and coordinated way. Our approach manages to reduce significantly the energy overhead associated to both variability and application dynamism (up to 50% according to our simulations) without compromising the application timing constraints