Anura P. Jayasumana

Virtual Sensor Networks - A Resource Efficient Approach for Concurrent Applications

Current focus of sensor networks is on systems dedicated for a specific application. Wide variety of circumstances point to the need for sensor network deployments capable of sharing the physical network resources. We introduce the concept of virtual sensor networks (VSN) to provide protocol support for the formation, usage, adaptation and maintenance of subsets of sensors collaborating on specific tasks. VSN concept also promises to enhance applications that involve dynamically varying subsets of sensor nodes collaborating tightly to achieve the desired outcomes, while relying on the remaining nodes to achieve connectivity and overcome the deployment and resource constraints. This article explores the concept, mechanisms, and benefits of using VSN. Examples of VSN support functionality include support for nodes to join and leave VSNs, broadcast within a VSN, and merging of VSNs. VSNs will simplify application deployment, enhance performance and scalability, facilitate resource sharing, and provide a degree of physical topology independence in wireless sensor networks. Deployment of overlapping sensor networks aimed at different tasks, especially in harsh environments, will also significantly benefit when organized as VSNs over a shared infrastructure

Effect of hidden terminals on the performance of IEEE 802.11 MAC protocol

The hidden terminal problem is unique to wireless networks and as of now there is very limited understanding about its effects on network performance. Results are presented from a simulation study of the IEEE 802.11 MAC protocol when operating in the presence of hidden terminals. We also propose a framework for modeling hidden terminals which can handle complex scenarios of both mobility and static obstructions. Our simulations indicate that hidden terminals can have a very detrimental effect on the performance of the IEEE 802. 11 MAC protocol. Although the throughput is acceptable when about 10 percent of station pairs are hidden, the packet delay can increase by an order of magnitude. The performance of the protocol drops sharply when the number of hidden pairs exceeds 10 percent.

Clustering based techniques for I/sub DDQ/ testing

A new technique for evaluating I/sub DDQ/ data using a clustering based approach is presented. While prevailing I/sub DDQ/ test techniques rely on a fixed threshold or the current signature of an IC, the proposed technique relies on abnormalities of the I/sub DDQ/ distribution of a device with respect to other devices in the test set. Results of applying this technique to data collected on a high volume graphics chip are described. Results are also compared to the conventional single threshold approach, and benefits of the new technique are presented.

Zonal rumor routing for wireless sensor networks

Routing algorithms for wireless sensor networks are constrained by power, memory and computational resources. Rumor routing algorithm for sensor-networks spreads the information of an event to other nodes in the network, thus enabling queries to discover paths to the events. Zonal rumor routing (ZRR) is an extension to the rumor routing algorithm. ZRR algorithm enables the rumors to spread to a larger part of the network with high energy efficiency by partitioning the network into zones. New algorithm improves the percentage query delivery and requires fewer transmissions, thus reducing the total energy consumption in a sensor network. Rumor routing can be considered as a special case of ZRR when only one node belongs to one zone. The performance of ZRR, the effect of zone size, and the scalability of the algorithm are evaluated using simulations.

On the use of the IEEE 802.4 token bus in distributed real-time control systems

The performance of the IEEE 802.4 priority mechanism in handling distributed real-time control traffic is examined. A timer assignment technique is presented for such applications. The timers are set to satisfy the worst-case access delay requirements of real-time control applications. Other applications that are not time constrained can be supported simultaneously. Under certain conditions, such applications can also be guaranteed a minimum bandwidth allocation. Simulation results are used to evaluate the timer assignment scheme. >

Pass-transistor logic design

Logic functions implemented using CMOS transmission gates provide a moderate improvement in area and speed over logic gate implementations. Several techniques for the implementation of pass transistor logic are presented. These techniques use only nMOS transistors in the pass network. The output logic level is restored using additional circuitry. The proposed designs require less silicon area, less power dissipation, and operate at higher speeds compared with the conventional CMOS pass-transistor networks. The speed of operation depends mainly on the circuitry used to restore the output signal of the pass network. The different techniques are compared with respect to the layout area and operating speed.

On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates

Bridging faults have been shown to be a major failure mode in VLSI devices. This study examines nMOS and CMOS complex gates in detail for bridging faults. Analysis is carried out using both switch and circuit level models for comparison. It is shown that in most cases, the switch level analysis predicts the correct behavior. A set of conditions are presented, under which the switch level analysis may fail to predict the correct behavior. These conditions can be used for accurate switch level test generation and simulation.

Throughput analysis of the IEEE 802.4 priority scheme

The IEEE 802.4 token bus standard defines an optional priority scheme to handle multiple classes of data. It allocates the channel bandwidth among different priority classes of messages by a set of timers at each station. An analytical model for the priority scheme is presented. The model relates the throughput of each priority class of messages to the traffic intensities of different classes, the target rotation times, and the high-priority token holding time. The network is assumed to be symmetric with respect to its parameters and the traffic distribution among nodes. Simulation results are used to evaluate the accuracy of the model. The model provides means of evaluating the network throughput and can be used to determine the time values to meet the throughput requirements of different classes of traffic. >

Collaborative applications over peer-to-peer systems–challenges and solutions

Emerging collaborative Peer-to-Peer (P2P) systems require discovery and utilization of diverse, multi-attribute, distributed, and dynamic groups of resources to achieve greater tasks beyond conventional file and processor cycle sharing. Collaborations involving application specific resources and dynamic quality of service goals are stressing current P2P architectures. Salient features and desirable characteristics of collaborative P2P systems are highlighted. Resource advertising, selecting, matching, and binding, the critical phases in these systems, and their associated challenges are reviewed using examples from distributed collaborative adaptive sensing systems, cloud computing, and mobile social networks. State-of-the-art resource discovery/aggregation solutions are compared with respect to their architecture, lookup overhead, load balancing, etc., to determine their ability to meet the goals and challenges of each critical phase. Incentives, trust, privacy, and security issues are also discussed, as they will ultimately determine the success of a collaborative P2P system. Open issues and research opportunities that are essential to achieve the true potential of collaborative P2P systems are discussed.

Design of CMOS circuits for stuck-open fault testability

A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes. >