Anurag Jindal

STRUCTURAL TESTING OF INTEGRATED CIRCUITS

Integrated circuit with increased fault coverage

Data retention flip-flop

INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF

METHOD AND SYSTEM FOR LOGIC BUILT-IN SELF-TEST

BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL

LBIST DEBUG CONTROLLER

Scan wrapper circuit for integrated circuit

RESET GENERATION CIRCUIT FOR SCAN MODE EXIT

INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS