Apostolos A. Kountouris

Efficient scheduling of conditional behaviors for high-level synthesis

As hardware designs get increasingly complex and time-to-market constraints get tighter there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both dataflow-dominated and controlflow-dominated designs as well as designs of a mixed nature. In the past efficient tools for the former type have been developed but so far HLS of conditional behaviors lags behind. To bridge this gap an efficient scheduling heuristic for conditional behaviors is presented. Our heuristic and the techniques it utilizes are based on a unifying design representation appropriate for both types of behavioral descriptions, enabling the proposed heuristic to exploit under the same framework several well-established techniques (chaining, multicycling) as well as conditional resource sharing and speculative execution which are essential in efficiently scheduling conditional behaviors. Preliminary experiments confirm the effectiveness of our approach and prompted the development of the CODESIS HLS tool for further experimentation.

Hierarchical conditional dependency graphs for conditional resource sharing

Conditional resource sharing has been identified as a possibility for optimizing high-level synthesis results. We propose a hierarchical conditional dependency graph representation that permits to treat conditional resource sharing in a generic fashion depending on the specific context, i.e. functional units, storage elements and interconnects. Resource usage conditions are represented in a control hierarchy of BDD trees that permits efficient reasoning on condition exclusiveness. These ideas are illustrated by a scheduling example.

Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system

In high-level hardware synthesis (HLS) there is a gap on the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors, are encouraging and prompt for more extensive experimentation.

False path analysis based on a hierarchical control representation

False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time estimation, software testing etc. In this paper a method to automate false path analysis, based on a control flow graph connected to a hierarchical BDD based control representation, is described. By its ability to reason on predicate expressions involving arithmetic inequalities, this method overcomes certain limitations of previous approaches. Preliminary experimental results confirm its effectiveness.

Hierarchical conditional dependency graphs for mutual exclusiveness identification

Identifying operation mutual exclusiveness is important in order to improve the quality of high-level synthesis results, by reducing either the required number of control steps or the needed hardware resources by conditional resource sharing. To this end we propose the hierarchical conditional dependency graph representation and an algorithm for identification of mutually exclusive operations. A hierarchical control organization permits one to minimize the number of pair-wise exclusiveness tests during the identification process. Using graph transformations and reasoning on arithmetic inequalities, the proposed approach can produce results independent of description styles and identify more mutually exclusive operation pairs than previous approaches.

Combining speculative execution and conditional resource sharing to efficiently schedule conditional behaviors

Scheduling conditional behaviors necessitates the use of a variety of scheduling optimization techniques like conditional resource sharing and speculative execution. Previous research work has clearly shown their effectiveness. The developed heuristics have several drawbacks relating to the effects of syntactic variance on the results. In this paper a list-based scheduling heuristic that exploits conditional resource sharing and speculative execution possibilities, is presented. Its results are quite insensitive to syntactic variance and conditional behavior is effectively accounted for by a probabilistic priority function.

High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system

In previous work in behavioral high-level synthesis (HLS), data-flow and control-flow dominated descriptions are treated separately. A result of such a separation is that efficient techniques have been developed for the HLS of data-flow dominated behavioral descriptions. However, HLS of control-flow dominated descriptions still lags behind. To close this gap in this paper we propose a complete HLS framework based on an internal design representation where control- and data-flows are uniformly represented and disposes a formal foundation. Based on it conditional behaviors can be efficiently scheduled combining conditional resource sharing (CSR), speculative execution (SE) and other formal graph transformations. These techniques and tools covering all HLS activities have been organized in the CODESIS tool destined for both research and educational purposes.

Throughput Capacity Analysis of a Random Multi-user Multi-channel Network Modeled as an Occupancy Problem

In this paper, we model the random multi-user multi-channel access network by using the well known occupancy problem from probability theory. Furthermore, we combine this with a network interference model in order to derive the achievable throughput capacity of such networks. The mathematical developments and results are illustrated through various simulations results. The proposed model is particularly relevant in analyzing the performance of networks where the users are not synchronized neither in time nor in frequency as it is often the case in various Internet of Things (IoT) applications.

Sub-sampling of channels with time and frequency sparsity access

This paper shows that sub-sampling of signals can help in reducing the amount of data to be processed and stored when time and frequency sparsity is considered. The context is the one of the Internet of Things (IoT) for which a huge quantity of users (i.e. objects) communicate with very few time and frequency accesses. Taking advantage of the occupancy theory of probabilities, we propose a theoretical model for such communications and we show that the sampling frequency of signals can be significantly reduced under these assumptions.